參數(shù)資料
型號(hào)： UPD46128953-X
廠商： NEC Corp.
英文描述： 128M-BIT CMOS MOBILE SPECIFIED RAM 4M-WORD BY 32-BIT ADDRESS / DATA MULTIPLEXED EXTENDED TEMPERATURE OPERATION
中文描述： 128兆位CMOS移動(dòng)指明內(nèi)存分詞由32位地址/數(shù)據(jù)復(fù)用溫度范圍
文件頁數(shù)： 36/60頁
文件大小： 468K
代理商： UPD46128953-X
Preliminary Data Sheet M17506EJ1V1DS
36
μ
PD46128953-X
5. 5 Write data mask signal (DM) control
This section explains how to control the write data mask signal (DM). DM is a signal that masks input data.
Data mask is valid only in the write cycle. Therefore, data can be masked in the burst write cycle but cannot in the
burst read cycle.
The write data mask signal (DM) controls byte unit with one pin.
- DM0 controls A/DQ7 to A/DQ0.
- DM1 controls A/DQ15 to A/DQ8.
- DM2 controls A/DQ21 to A/DQ16 and DQ23 to DQ22.
- DM3 controls DQ31 to DQ24.
5. 5. 1
Controlling write data mask signal (DM) in write cycle
As shown in
Figure 5-10
, the corresponding write data is masked when the write data mask signal (DM) is HIGH.
Figure 5-10. Command Loading Timing 1
T0
T1
T2
/ADV (Inout)
/WE (Input)
CLK (Input)
A/DQ0 to A/DQ21 (Input)
High-Z
D0
Add
T3
T4
T5
T6
T7
DM (Input)
Mask
D2
Mask
D4
DQ22 to DQ31 (Input)
High-Z
D0
Mask
D2
Mask
D4
t
BDS
t
BDH
t
BDH
t
BDS
Remark
Refer to
6. Electrical Specifications
,
7. Timing Charts
in detail of AC specification
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