參數(shù)資料
型號： UPD46128953-X
廠商： NEC Corp.
英文描述： 128M-BIT CMOS MOBILE SPECIFIED RAM 4M-WORD BY 32-BIT ADDRESS / DATA MULTIPLEXED EXTENDED TEMPERATURE OPERATION
中文描述： 128兆位CMOS移動指明內(nèi)存分詞由32位地址/數(shù)據(jù)復(fù)用溫度范圍
文件頁數(shù)： 27/60頁
文件大小： 468K
代理商： UPD46128953-X
Preliminary Data Sheet M17506EJ1V1DS
27
μ
PD46128953-X
4. 2 Mode Register Reading
If 0 is set to A/DQ0 in the 4th cycle after reading the most significant address (3FFFFFH) – two consecutive cycles for
writing any data, it is possible to read current setting value of code 2 in the 5th cycle and current setting value of code 3 in
the 6th cycle
Table 4-5. Mode Register Settings
Cycle
Operation
Address
Data
1st cycle
Read
3FFFFFH
Don’t care
2nd cycle
Write
3FFFFFH
Don’t care
3rd cycle
Write
3FFFFFH
Don’t care
4th cycle
Write
3FFFFFH
Code 1 (A/DQ0 = 0)
5th cycle
Read
3FFFFFH
Code 2
6th cycle
Read
3FFFFFH
Code 3
Codes 1 to 3 are written to the register. The register has a function to latch an address and data necessary for
instruction execution, and does not occupy the memory.
For the timing chart and flowchart, refer to
Figure 8-3. Mode Register Read Timing Chart
and
Figure 8-4. Mode
Register Read Flowchart
.
4. 2. 1
Cautions for Setting Mode Register
When the mode register is set, the status of the internal counter is identified by the toggle operation of /CE1 and /OE.
When setting the mode register, therefore, perform a toggle operation of /CE1 in each cycle (one read cycle, three write
cycles, and two mode register read cycles). In the 1st bus cycle (read cycle) and 5th and 6th bus cycles, perform a
toggle operation of /OE in the same manner as /CE1. If an illegal address or data is written or if the codes are written in
an incorrect sequence, reading the mode register fails and the mode register is not read correctly.
If the most significant address (3FFFFFH) is read (in the 1st bus cycle), written (2nd bus cycle), and then written (3rd
bus cycle), a sequence of setting/reading the mode register is started. Therefore, setting of the mode register cannot be
stopped after the 4th bus cycle. If the normal sequence is executed up to the 3rd bus cycle, setting of the mode register
cannot be stopped until the 6th bus cycle is completed.
4. 2. 2
Data read from mode register
If reading the mode register is started, the contents of currently set code 2 (partial refresh density, burst length, function
mode, and driver strength) can be read in the 5th bus cycle. In the 6th bus cycle, the contents of currently set code 3
(read latency, single write, valid clock edge, reset to asynchronous, and /WE control) can be read. If the mode register is
read before it is set, any (undefined) data is output.
Set or read the mode register in compliance with the AC specifications in Table 4-6.
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