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參數(shù)資料
| 型號： | TNETA1560 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | ATM Segmentation and Reassembly Device with SBUS Host Interface(ATM 分段和重設裝置帶SBUS主機接口) |
| 中文描述： | 自動柜員機分段和重組與SBus主機接口（自動柜員機分段和重設裝置帶SBU的主機接口設備） |
| 文件頁數(shù)： | 37/40頁 |
| 文件大小： | 804K |
| 代理商： | TNETA1560 |
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TNETA1560
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH SBUS HOST INTERFACE
SDNS010C – JANUARY 1994 – REVISED OCTOBER 1995
37
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
EN_TX – enable transmit operation
The EN_TX bit allows the host to disable packet-to-cell segmentation and any payload data transfer from the
It is set to zero on reset, disabling transmit operation until various configuration register, the BWG table, and
the DMA blocks are configured by the host. The transfer of the new cells from SBus to the SAR is inhibited when
the enable-transmit bit is disabled; however, cells already in the output buffer are forwarded to the PHY layer.
EN_RX – enable receive operation
The EN_RX bit allows the host to disable packet reassembly. All cells from the PHY layer are dropped when
the EN_RX bit is zero. The EN_RX bit is set high to enable normal processing. It is set to zero on reset, disabling
receive operation until various configuration and the DMA blocks are reconfigured by the host. The transfer of
new cells from the ATM link to the receive buffer is inhibited when the enable receive bit is disabled.
NCE mode indicator
The NCE bit is set to indicate to the SAR that cell payloads must be transferred exclusively via 16-byte SBus
bursts. The value at the input of the NCE-mode terminal is shifted into this indicator bit on every clock cycle.
Internal operation of the SBus SAR is based on the value of this register.
status register
The SAR status register is read only for the host. All the bits except the TX_freeze bit and the SBus error flags
are cleared when the register is read. The SAR generates an SBus interrupt to the host if one of the bits in the
register is set and if the condition represented by the bit is enabled by the interrupt-enable-mask register. The
SBus interrupt is an asynchronous signal that is held until the system clears the condition that caused the
interrupt.
Unused (bits 31 – 11)
LB_intr (bit 10)
SB_lerr (bit 9)
SB_err_ack (bit 8)
RX_freeze (bit 7)
TX_freeze (bit 6)
TX_comp_notav (bit 5)
RX_comp_notav (bit 4)
RX_bfree_notav (bit 3)
RX_sfree_notav (bit 2)
TX_comp_update (bit 1)
RX_comp_update (bit 0)
TX_comp_update, RX_comp_update (bits 1 – 0)
The transmit or receive completion update bit is set when the hardware releases a transmit or receive descriptor,
respectively, to the completion ring. This is initiated when the OWN bits in the respective DMA blocks are cleared
by the SAR.
RX_bfree_notav, RX_sfree_notav (bits 3 – 2)
The appropriate receive free-buffer not-available bit is set when the first entry in the corresponding receive
free-buffer ring is not available. This is indicated when the OWN bit in the first entry of the free ring is zero.
The incoming cell is deleted since there is no buffer available in which to place it. This eventually causes the
loss of the entire packet due to the resultant CRC error. The buffer-allocation-error bit in the DMA block is set,
indicated by a zero in the first free-buffer-ring entry.
RX_comp_notav (bit 4)
The receive completion-ring not-available bit is set when the next descriptor in the receive completion ring has
not been released by the host. This is indicated when the OWN bit in the entry is zero. This packet and buffer
are both lost to host memory.
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