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| 型號： | TNETA1560 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | ATM Segmentation and Reassembly Device with SBUS Host Interface(ATM 分段和重設(shè)裝置帶SBUS主機(jī)接口) |
| 中文描述： | 自動柜員機(jī)分段和重組與SBus主機(jī)接口（自動柜員機(jī)分段和重設(shè)裝置帶SBU的主機(jī)接口設(shè)備） |
| 文件頁數(shù)： | 15/40頁 |
| 文件大?。?/td> | 804K |
| 代理商： | TNETA1560 |
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TNETA1560
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH SBUS HOST INTERFACE
SDNS010C – JANUARY 1994 – REVISED OCTOBER 1995
15
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
operating characteristics (see Figure 9)
NO.
MIN
TYP
MAX
UNIT
1
tw(CMR/WL)
td(CMR/W)1
td(CMR/W)2
td(CMD)
Pulse duration, CMR/W low
40
ns
2
Delay time, CMADDR13–CMADDR0 valid to CMR/W
↓
20
ns
3
Delay time, CMD31–CMD0 valid to CMR/W
↑
60
ns
4
Delay time, CMR/W
↑
to CMD31–CMD0 invalid
20
ns
The typical values are given for operation with a 25-MHz SBus clock.
CMOE
(output)
CMADDR13–
CMADDR0
(output)
2
CMD31–
CMD0
(output)
1
4
Valid
Valid
Invalid
CMR/W
(output)
3
Figure 9. Control-Memory-Interface Write Operation
timing requirements (see Figure 10)
NO.
MIN
MAX
UNIT
1
tsu(CMD)
th(CMD)
Setup time, CMD31–CMD0 valid before CMOE
↑
9
ns
2
Hold time, CMD31–CMD0 valid after CMOE
↑
2
ns
These values are given for operation with a 25-MHz SBus clock.
operating characteristics (see Figure 10)
NO.
MIN
TYP
MAX
UNIT
3
td(CMOE)
Delay time, CMADDR13–CMADDR0 valid to CMOE
↓
1
ns
The typical values are given for operation with a 25-MHz SBus clock.
CMR/W
(output)
CMADDR13–
CMADDR0
(output)
3
CMD31–
CMD0
(input)
Valid
Valid
CMOE
(output)
1
2
Figure 10. Control-Memory-Interface Read Operation
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