參數(shù)資料
型號(hào)： TNETA1560
廠商： Texas Instruments, Inc.
英文描述： ATM Segmentation and Reassembly Device with SBUS Host Interface(ATM 分段和重設(shè)裝置帶SBUS主機(jī)接口)
中文描述： 自動(dòng)柜員機(jī)分段和重組與SBus主機(jī)接口（自動(dòng)柜員機(jī)分段和重設(shè)裝置帶SBU的主機(jī)接口設(shè)備）
文件頁(yè)數(shù)： 19/40頁(yè)
文件大?。?/td> 804K
代理商： TNETA1560
TNETA1560
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH SBUS HOST INTERFACE
SDNS010C – JANUARY 1994 – REVISED OCTOBER 1995
19
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
AAL5 processing
The primary support is for AAL5 with encapsulation in the transmit direction and termination in the receive
direction. The AAL5 packets are converted to cells by the SBus SAR before delivery to the PHY layer. Similarly,
the device recovers 53-byte ATM cells from the PHY layer before it performs AAL5 termination.
The SBus SAR adds the pad, the control/length field, and the cyclic redundancy check (CRC) for transmit
packets. The SBus SAR does not interpret the field length in the AAL5 frame in the receive direction; therefore,
the entire AAL5 packet is forwarded to host memory allowing the driver to remove the correct payload. This also
allows the host to examine the control field in software, necessary in a time of evolving standards in this area.
The device performs CRC checks in the receive direction and indicates EOP processing to the host based on
the EOP indication in AAL5.
null-AAL processing
Null-AAL processing uses the same mechanism as the AAL3/4 in the transmit direction to disable AAL5
processing. The control entry associated with each BWG (VCI) in the receive direction has an entry to indicate
an interval defined in units of cells received. The SBus SAR then provides an interrupt to the host when the
number of cells received on the VCI is equal to that indicated by the table entry. This counter is reset after each
interrupt (at the end of each interval). This interval is also referred to as a packet, although it does not
encapsulate a well-defined unit of information.
high-order VPI/ VCI bits GFC processing
The lower ten bits of the VCI are used to encode the 1023 possible VCIs. VCI 0 is not used since it indicates
unassigned cells. The upper-order bits of the VCI and the VPI field are programmable on a per-VC basis on
transmit. The GFC field is always set to zero.
The upper-order bits of the VCI, the VPI field, and the GFC field are ignored on all cells that are received. These
cells pass to the SBus SAR if the header-error-control (HEC) field is correct, the upper-order bits of the header
are set intentionally, or the cell is misrouted. The probability of misrouting is small and such an event would be
detected via the CRC check in AAL5. The advantage of this scheme is that any VPI/VCI combination is
supported if the lower ten bits of the VCI are unique.
OAM processing
The ATM-layer OAM processing does not require any real-time intervention and is processed in software. OAM
cells received on the link must be identified by the device. Table 1 summarizes ATM-layer OAM encoding as
described by various standards bodies.
Table 1. ATM-Layer OAM Encoding
NO.
ITEM
VCI
PTI
1
VP level: link-associated OAM cell
3
—
2
VP level: end-to-end OAM cell
4
—
3
VC level: link-associated OAM cell
Any
4
4
VC level: end-to-end OAM cell
Any
5
Each OAM cell forms a fully encapsulated packet. The ATM-layer OAM cells transcend AAL protocols and are
recognized differently. The end system recognizes all four ATM-layer OAM flows. OAM cells received in
VCI 3 and 4 do not interfere with the normal data stream. The only special processing necessary is to initiate
EOP processing for each cell. The software drivers must configure VCI 3 and 4 as null-AAL channels with a
packet length equal to one cell in the receive direction. OAM cells are transmitted as null-AAL packets with
length equal to one cell. VC-level OAM cells are specially interpreted. They are diverted to receive
direct-memory access (DMA) channel 0 and the 4-byte ATM header is passed on to a receive completion ring
in host memory during normal EOP processing.
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