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| 型號： | TNETA1560 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | ATM Segmentation and Reassembly Device with SBUS Host Interface(ATM 分段和重設(shè)裝置帶SBUS主機接口) |
| 中文描述： | 自動柜員機分段和重組與SBus主機接口（自動柜員機分段和重設(shè)裝置帶SBU的主機接口設(shè)備） |
| 文件頁數(shù)： | 31/40頁 |
| 文件大小： | 804K |
| 代理商： | TNETA1560 |
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TNETA1560
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH SBUS HOST INTERFACE
SDNS010C – JANUARY 1994 – REVISED OCTOBER 1995
31
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
TX DMA word 4 – descriptor-ring address (continued)
The address of the 4K-byte boundary in host memory is provided by bits (31 – 12). The entry number between
0 and 255 is provided by bits (11 – 4). The low-order four bits are set to zero and each entry is 16 byte aligned.
Bits (11 – 0) are initialized by the host to zero to correspond with the first entry used by the host in the transmit
data-descriptor ring.
TX DMA word 5 – place holder
Place holder (bits 31 – 0)
TX DMA word 6 – transmit CRC
Partial AAL5 transmit CRC (bits 31 – 0)
This field stores the 32-bit CRC calculated over the entire payload of each AAL5 packet. The CRC is placed
in the last four bytes of the last cell of the corresponding packet.
TX DMA word 7 – AAL5 tail
AAL5 control field (bits 31 – 16)
AAL5 length field (bits 15 – 0)
The AAL5 control and length fields are copied directly from the corresponding transmit data-descriptor entry
at the start of each new packet. The length field is not used for any control functions within the SAR. Both fields
are used exclusively for placement in the tail of an AAL5-protocol data unit (PDU).
transmit completion ring
Table 8 shows the composition of the 4-word entry. The transmit completion ring is a free ring with 256 entries.
The SAR posts an item to the next entry in the completion ring when it completes the transmission of each
packet. The transmit-completion-ring pointer maintains the value of the current entry within the SAR. The host
can recalibrate to this by reading the value from the initialization section in control memory.
Table 8. Transmit-Completion-Ring Summary
ENTRY
DESCRIPTION
Word 0
OWN (bit 31)
Unused (bits 30 – 8)
BWG index (bits 7 – 0)
Word 1
Reserved
Word 2
Reserved
Word 3
Reserved
TX completion-ring word 0
OWN (bit 31)
This completion-ring entry is owned by the SBus SAR when the OWN bit is set. The completion-ring entry is
owned by the host when the OWN bit is zero. The SAR uses the next completion-ring entry in the ring if the OWN
bit is set. The TNETA1560 clears the OWN bit after updating the entry. The host then receives an interrupt and
retrieves the next entry in the completion ring to post the completion of packet transmission for a BWG and the
release of the buffer space occupied by the buffers constituting the packet. The host clears the OWN bit to allow
the SAR to use the completion-ring entry. If the OWN bit is not set when the SAR is ready to post a completed
packet, a status bit is set in the hardware-status register and an interrupt is generated if the error condition is
unmasked.
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