參數(shù)資料
型號(hào)： TNETA1560
廠商： Texas Instruments, Inc.
英文描述： ATM Segmentation and Reassembly Device with SBUS Host Interface(ATM 分段和重設(shè)裝置帶SBUS主機(jī)接口)
中文描述： 自動(dòng)柜員機(jī)分段和重組與SBus主機(jī)接口（自動(dòng)柜員機(jī)分段和重設(shè)裝置帶SBU的主機(jī)接口設(shè)備）
文件頁(yè)數(shù)： 21/40頁(yè)
文件大?。?/td> 804K
代理商： TNETA1560
TNETA1560
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH SBUS HOST INTERFACE
SDNS010C – JANUARY 1994 – REVISED OCTOBER 1995
21
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
Table 2. SBus Transactions
NO.
TRANSACTION TYPE
SAR
ROLE
Slave
TRANSFER
SIZE
Word
ACK.
SIZE
Word
1
Host accesses SAR registers or control memory
2
Host accesses PHY-layer registers
Slave
Word
Word
3
Host accesses EPROM
Slave
Byte/Word
Byte
4
SAR transmits control-information transactions and receives free-buffer ring transac-
tions
SAR receive completion-ring entries posted to the host
Master
Word
Word
5
Master
4 Word
4 Word
6
SAR cell-payload transfers (default)
Master
8, 4, and 1 Word
8, 4, and 1
Word
4 Word
7
SAR cell-payload transfers (NCE)
Master
4 Word
It is efficient to transfer the 48-byte payload via successive transfers of 32 and 16 bytes if the data is on even
burst boundaries. This is the algorithm followed by the SAR in the default mode for all transfers on receive and
for all transfers on transmit except those on buffer boundaries.
The NCE is based on a SPARC station 1+ platform that does not support 32-byte bursts. A configuration register
bit on the SBus SAR programmed by the host is set to indicate that the platform is the NCE or any system that
does not support 32-byte bursts. The device then uses 16-byte bursts exclusively to transfer cell-payload data
in each direction.
Since there is at least a 4-cycle overhead associated with each transfer for a DVMA master, the number of cycles
required to transfer a cell in the default mode in either direction with no overhead for packet processing is at least
20 SBus cycles. The time to transfer the 48-byte cell payload on the NCE in either direction is at least 24 SBus
cycles.
SBus interaction and burst-transfer size requirements (continued)
Burst transfers in the transmit direction are optimized to yield the fewest SBus cycles based on buffer, packet,
cell boundaries, and their location in host memory.
commands, registers, and interrupts
The SBus SAR has several internal registers for configuration and storage of operational-state information. The
information contained in the registers is described in a later section.
The SAR generates an interrupt, connected on the adapter to SBIRQ, on packet completion and on a variety
of error conditions.
PHY data interface
The ATM-cell-transfer rate is full-duplex 149.76 Mbit/s, but data may arrive in bursts at 155.52 Mbit/s due to the
framing scheme described by the PHY layer. A clock rate of at least 19.44 MHz is essential in the receive
direction to prevent cell loss due to buffer overflow in the PHY layer. The SBus SAR decouples the SBus clock
from the ATM clock in the receive direction via an asynchronous FIFO memory, which holds up to 32 cells. The
SAR transmits data to the PHY layer at the SBus clock rate.
PHY-layer control interface
Figure 11 shows that the local bus is used to connect the SBus EPROM to the register interface on the PHY-layer
device.
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