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參數(shù)資料
| 型號： | TNETA1560 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | ATM Segmentation and Reassembly Device with SBUS Host Interface(ATM 分段和重設(shè)裝置帶SBUS主機(jī)接口) |
| 中文描述： | 自動柜員機(jī)分段和重組與SBus主機(jī)接口（自動柜員機(jī)分段和重設(shè)裝置帶SBU的主機(jī)接口設(shè)備） |
| 文件頁數(shù)： | 22/40頁 |
| 文件大小： | 804K |
| 代理商： | TNETA1560 |
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TNETA1560
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH SBUS HOST INTERFACE
SDNS010C – JANUARY 1994 – REVISED OCTOBER 1995
22
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
interfaces
The terminal layout and the terminal functions table fully describe the terminal assignments and functions of
the Sbus SAR (TNETA1560).
SBus interface
The SBus SAR behaves both as an SBus DVMA master and slave. The SBus SAR is selected as the slave if
the SBSEL signal is asserted. The system accesses the control-memory block, the local bus, and the user
registers with SBus slave accesses to the SAR. The transfer size is determined by SBSIZ2–SBSIZ0, which must
be set to 000 to represent a 1-word transfer. The physical address is given by the SBPA signals and must fall
within the ranges specified in Tables 4 and 13. The SBus SAR generates an error acknowledgment given by
SBACK2–SBACK0 set to 110 if either of these two conditions is violated. The SBAS signal is used as described
in the SBus specification, and the SBRD signal indicates a read or write operation. Finally, SBACK2–SBACK0
are set to 011 to indicate SBus word acknowledgment for operations on the SAR registers and control memory;
SBACK2–SBACK0 are set to 101 to indicate SBus byte acknowledgment on host accesses to the EPROM via
the local bus.
The SBus SAR can initiate transactions as master only when no slave transactions are active. The SAR asserts
the dedicated SBBR signal to request an operation as the SBus master. The SBus controller asserts the SAR
dedicated SBBG signal making the SAR the master. The SAR sets the SBSIZ2–SBSIZ0 signals to indicate a
1-word, 16-byte, or 32-byte transfer, the SBRD signal indicates a read or write operation, and the DVMA address
is placed on the SBD31–SBD0 lines. The TNETA1560 monitors the SBACK2–SBACK0 lines anticipating the
appropriate acknowledgment value. The SBus SAR considers either an error acknowledgment on the
SBACK2–SBACK0 lines or a late error on the SBLERR line as a fatal error, disables all data-transfer processing,
and generates a SBus interrupt via the SBIRQ signal.
control-memory interface
The control memory is set up in a 16K
×
32 configuration with the cycle time given by the SBus clock. The
interface is designed for an asynchronous SRAM with a 32-bit data bus, a 14-bit address bus, a CMR/W signal
determine read or write, and an output-enable signal (CMOE).
PHY-layer interface
The SBus SAR generates a transmit clock at the SBus frequency and a 19.44-MHz receive clock. This ensures
that all setup- and hold-time restrictions are met.
The SBus SAR generates output data along with a start-of-cell indicator in the transmit direction. This data is
sent at the rate of the SBus clock. The PHY layer can respond with a full signal, which is asserted at least four
cycles before any internal buffers are full. The SAR then turns off TXENABLE until the full signal is deasserted.
The PHY layer sends a start-of-cell indicator with output data. The empty signal acts as an inverted enable signal
on this interface.
The PHY-layer interrupt signal is directly connected to the SBus interrupt signal; therefore, the SBus interrupt
is asserted when the PHY-layer interrupt signal is asserted.
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