參數(shù)資料
型號(hào)： TNETA1560
廠商： Texas Instruments, Inc.
英文描述： ATM Segmentation and Reassembly Device with SBUS Host Interface(ATM 分段和重設(shè)裝置帶SBUS主機(jī)接口)
中文描述： 自動(dòng)柜員機(jī)分段和重組與SBus主機(jī)接口（自動(dòng)柜員機(jī)分段和重設(shè)裝置帶SBU的主機(jī)接口設(shè)備）
文件頁數(shù)： 26/40頁
文件大?。?/td> 804K
代理商： TNETA1560
TNETA1560
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH SBUS HOST INTERFACE
SDNS010C – JANUARY 1994 – REVISED OCTOBER 1995
26
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
programmer’s reference (continued)
Each descriptor ring has 256 entries as shown in Figure 15. Each descriptor-ring entry consists of four words.
Each descriptor ring is aligned to a 4K-byte boundary in host memory with each entry aligned to a 16-byte
boundary. The SAR has two receive free-buffer rings, one transmit completion ring, and one receive completion
ring. The current pointer to each of these rings is stored in the initialization block in SAR control memory. An
entry in each transmit DMA channel points to one of the 255 transmit-descriptor rings in host memory.
Each DMA-channel entry consists of eight words and is located in control memory. The DMA entries on both
transmit and receive have an OWN bit that is set when the DMA channel is active. The descriptor-ring entries,
the completion-ring entries, and the free-buffer-ring entries have an OWN bit that is set when the entry belongs
to the SAR.
control-memory map and access
Table 4 shows a control-memory map. The address bus to memory is 14 bits wide. The physical SBus offset
address on the SAR for control memory is C00000 hex. All SBus accesses to control are 1-word accesses at
word boundaries.
Table 4. Control-Memory Map
MEMORY REGIONS
CONTROL-MEMORY
BASE POINTERS (hex)
0000
SBus PHYSICAL
ADDRESS (hex)
C00000
Initialization block
Transmit BWG 0 – 255 – DMA block
0100
C00400
BWG table (1200 words, 4800 entries)
0900
C02400
Receive BWG/VCI 0 – 1023 – DMA block
1000
C04000
initialization block
The initialization block contains exactly four entries and resides in control memory. Table 5 shows the
configuration of the initialization block.
Table 5. Initialization Block
SBus PHYSICAL
ADDRESS (hex)
C00000
CONTROL-MEMORY
ADDRESS (hex)
0000
BITS 27 – 8
BITS 7 – 0
TX completion-ring offset pointer
Index 0 – 255
C00004
0001
RX completion-ring offset pointer
Index 0 – 255
C00008
0002
Small free-buffer-ring offset pointer
Index 0 – 255
C0000C
0003
Big free-buffer-ring offset pointer
Index 0 – 255
The pointers are mapped to SBus DVMA addresses by appending the lower-order four bits representing the
offset within each 16-byte descriptor-ring entry. Since accesses are only permitted on a word basis, the
lower-order two bits are always set to zero.
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