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參數(shù)資料
| 型號： | TNETA1560 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | ATM Segmentation and Reassembly Device with SBUS Host Interface(ATM 分段和重設裝置帶SBUS主機接口) |
| 中文描述： | 自動柜員機分段和重組與SBus主機接口（自動柜員機分段和重設裝置帶SBU的主機接口設備） |
| 文件頁數(shù)： | 29/40頁 |
| 文件大?。?/td> | 804K |
| 代理商： | TNETA1560 |
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TNETA1560
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH SBUS HOST INTERFACE
SDNS010C – JANUARY 1994 – REVISED OCTOBER 1995
29
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
transmit BWG DMA block
The control memory contains 255 transmit BWG DMA entries, each containing eight words. Table 7 summarizes
the contents of each entry.
Table 7. Transmit BWG DMA Entry
ENTRY
DESCRIPTION
STATIC/
DYNAMIC
Dynamic
Word 0
Control field, packet length, buffer length
Word 1
Current-buffer pointer – 32 bits
Dynamic
Word 2
4-byte ATM header
Dynamic
Word 3
Static bits – BWG ON/OFF (BWG_ON bit)
Static
Word 4
BWG data-ring pointer, descriptor pointer
Dynamic
Word 5
BWG cell-counter place holder – not implemented
Dynamic
Word 6
Partial 32-bit packet CRC
Dynamic
Word 7
AAL5 tail – control and length fields
Static
The SBus SAR initiates host transactions affecting the DMA table, except those required for one-time
configuration of a channel for normal operation based on cell-transmission opportunities from the BWG table.
Each DMA entry represents a buffer under segmentation.
During initialization, the host has to configure word 0, word 3, and word 4 in the transmit DMA states table for
each BWG selected for transmission in the BWG table, including the BWG0. These words allow the TNETA1560
to start a transmission of a new packet. After configuration, the TNETA1560 reads word 3 to check if the
BWG_ON bit is set. If it is set, the device reads word 0 to determine if the OWN bit is set. When the OWN bit
is not set, it indicates that this is the first buffer of a new packet. The TNETA1560 then reads word 4 to obtain
a transmit descriptor-ring pointer that indicates the memory address in host memory for the transmit
descriptor-ring pointer. The following sections explain each TX DMA table word in detail.
TX DMA word 0 – state/configuration
Control (bits 31 – 27)
Current-packet length (bits 26 – 16)
Current-buffer length (bits 15 – 0)
The contents of word 0 are copied directly from the corresponding transmit data-descriptor-ring entry at the start
of each new buffer. This applies to all the fields in this status word and the host must ensure consistency across
the fields.
OWN (bit 31)
The OWN bit is set when the DMA channel for the BWG is active and all related state information in the DMA
entry is current. The OWN bit indicates a packet is currently being segmented and transmitted for this BWG.
This OWN bit is cleared by the SAR after the entire packet is transmitted, a completion-ring entry is posted, and
an interrupt generated to the host.
The host sets the OWN bits for individual buffers in a packet in the transmit data-descriptor rings in order from
last to first. This ensures that the DMA block is not held up while waiting to acquire the next buffer from a partially
transmitted packet.
start of chain (SOC) (bit 30)
The SOC bit indicates that this is the first buffer of a packet which may consist of one or more buffers. This bit
is also set in packets with single buffers. The SOC bit is cleared by the SAR after all processing for the first buffer
is complete.
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