- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385942 > TNETA1560 (Texas Instruments, Inc.) ATM Segmentation and Reassembly Device with SBUS Host Interface(ATM 分段和重設(shè)裝置帶SBUS主機(jī)接口) PDF資料下載
參數(shù)資料
| 型號(hào)： | TNETA1560 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | ATM Segmentation and Reassembly Device with SBUS Host Interface(ATM 分段和重設(shè)裝置帶SBUS主機(jī)接口) |
| 中文描述： | 自動(dòng)柜員機(jī)分段和重組與SBus主機(jī)接口（自動(dòng)柜員機(jī)分段和重設(shè)裝置帶SBU的主機(jī)接口設(shè)備） |
| 文件頁數(shù)： | 3/40頁 |
| 文件大?。?/td> | 804K |
| 代理商： | TNETA1560 |
第1頁第2頁當(dāng)前第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁
TNETA1560
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH SBUS HOST INTERFACE
SDNS010C – JANUARY 1994 – REVISED OCTOBER 1995
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
SBus interface
TERMINAL
NAME
I/O
DESCRIPTION
NO.
SBACK2–
SBACK0
139–141
I/O
SBus acknowledge. SBACK2–SBACK0 are used to indicate SBus word acknowledgement for
word operations on the TNETA1560 registers and control memory if set to 011. If set to 101, the
SBus byte acknowledgement is for local bus operations. An error acknowledgement is indicated
if set to 110. SBACK2–SBACK0 can be driven by the system or by the TNETA1560 in slave mode.
SBAS
62
I
SBus address strobe. When SBAS is low, an address is loaded in the TNETA1560.
SBBG
61
I
SBus bus grant. SBBG is asserted by the SBus controller to make the TNETA1560 the master.
SBBR
59
O
SBus request. SBBR is asserted by the TNETA1560 to request operation as the SBus master.
SBCLK
57
I
SBus clock
SBD31–SBD0
66–69,
72–75,
78–81,
84–87,
90–93,
96–99,
102–105,
108–111
I/O
SBus data bus. SBD31–SBD0 provide access from the host to the contents of the TNETA1560
internal registers.
SBIRQ
63
O
SBus interrupt request. SBIRQ is asserted by the TNETA1560 to send an interrupt request to the
host.
SBLERR
146
I
SBus late error. SBLERR is considered a fatal error. SBLERR causes the TNETA1560 to terminate
the ongoing master-bus cycle. If SBLERR is a burst transfer, it completes the burst.
SBPA15–SBPA0
114–116,
119–123,
125–129,
131–133
I
SBus physical address. SBPA15–SBPA0 and SBPA22–SBPA23 provide the address for the host
to access the peripheral devices and the TNETA1560 internal registers via SBus slave-mode
transactions.
a sac o s
SBPA22–SBPA23
134–135
SBRESET
150
I
SBus reset. SBRESET is active low.
SBRD
138
I/O
SBus read. SBRD can be driven by the system or by the TNETA1560 when SBRD is operating as
the master. SBRD indicates a read when high and a write when low.
SBSEL
60
I
SBus select. SBSEL is active low and enables the host to access the TNETA1560 device.
SBSIZ2–SBSIZ0
143–145
I/O
SBus data-transfer size signals. SBSIZ2–SBSIZ0 are used to indicate the size of data transfers
between the TNETA1560 and the host.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TNETA1561 | ATM Segmentation and Reassembly Device with PCI Host Interface(ATM 分段和重設(shè)裝置帶SBUS主機(jī)接口) |
| TNETA1600 | SONET/SDH ATM Receiver/Transmitter for 622.08-Mit/s or 155.52-Mbit/s Operation(SONET/SDH ATM接收器/傳送器) |
| TNETA1610 | STS-12c/STM-4 Receiver/Transmitter with Clock Recovery/Generation(STS-12C/STM-4接收/傳送器) |
| TNETA1611 | STS-12c/STM-4 Receiver/Transimitter(STS-12C/STM-4接收/傳送器) |
| TNETA1630 | 622.08-MHz Clock-Recovery Device(622.08-MHz時(shí)鐘發(fā)生裝置) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TNETA1560MFP | 制造商:Rochester Electronics LLC 功能描述: 制造商:Texas Instruments 功能描述: |
| TNETA1560PGC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TNETA1561PGC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TNETA1570 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64-BIT PCI-HOST INTERFACE |
| TNETA1570MFP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ATM/SONET Segmentation and Reassembly Circuit |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。