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參數(shù)資料
| 型號： | TNETA1560 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | ATM Segmentation and Reassembly Device with SBUS Host Interface(ATM 分段和重設(shè)裝置帶SBUS主機(jī)接口) |
| 中文描述： | 自動柜員機(jī)分段和重組與SBus主機(jī)接口（自動柜員機(jī)分段和重設(shè)裝置帶SBU的主機(jī)接口設(shè)備） |
| 文件頁數(shù)： | 16/40頁 |
| 文件大?。?/td> | 804K |
| 代理商： | TNETA1560 |
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TNETA1560
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH SBUS HOST INTERFACE
SDNS010C – JANUARY 1994 – REVISED OCTOBER 1995
16
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
Architecture
Data Management
Programmer’s Reference
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Table of Contents
Functional Overview
Functional Description
Interfaces
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functional overview
The SBus SAR refers to an SBus device (TNETA1560) that provides an ATM interface. The device provides
an interface to SBus, ATM adaptation-layer processing, ATM SAR processing for full-duplex ATM at the STS-3c
rate of 155.52 Mbit/s, and the controls for the register interface on the physical (PHY) layer. Figure 11 shows
a typical connection to the SBus SAR in an adaptor-card application.
SBus
SAR
SBus
EPROM
Control
Memory
Physical
Layer
Media
8
32
Local Memory Bus
Local Slave Bus
S
Figure 11. SBus SAR External Connections
The SBus SAR provides a packet interface managed by descriptor rings, making the 53-byte ATM framing
format transparent to the user. The device passes the 48-byte payload of each cell across the SBus. All packets
are stored in host memory and accessed by the chip via the descriptor-ring mechanism.
The SBus SAR generates data in the transmit direction via a special bit-rate control table that provides explicit
cell-level interleaving between groups of VCs. This mechanism provides a high degree of flexibility in specifying
peak rates for each group, up to 155.52 Mbit/s at a resolution greater than 32 kbit/s. The VCs within a group
are serviced via a FIFO discipline on a per-packet basis.
The SBus SAR supports 1023 unique VCs, typically all associated with virtual path identifier (VPI) 0. The SBus
SAR allows multiple VPs with the caveat that each VC is unique. Limited support is provided to recognize
ATM-layer OAM cells.
The device is primarily intended for ATM adaptation-layer type 5 (AAL5) encapsulation and termination, which
is fully supported in hardware. Limited support is provided for ATM adaptation-layer type 3/4 (AAL3/4) with
48-byte transfers across the SBus interface and hardware recognition of the EOM indicator on the receive side.
Finally, a null AAL is also supported to facilitate real-time data transfer.
The interface to the PHY layer consists of an 8-bit-wide data path and associated control signals in both the
transmit and receive directions. The 53-byte ATM cells pass between the ATM and PHY layers.
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| TNETA1570 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64-BIT PCI-HOST INTERFACE |
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