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| 型號： | TNETA1560 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | ATM Segmentation and Reassembly Device with SBUS Host Interface(ATM 分段和重設(shè)裝置帶SBUS主機接口) |
| 中文描述： | 自動柜員機分段和重組與SBus主機接口（自動柜員機分段和重設(shè)裝置帶SBU的主機接口設(shè)備） |
| 文件頁數(shù)： | 1/40頁 |
| 文件大小： | 804K |
| 代理商： | TNETA1560 |
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TNETA1560
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH SBUS HOST INTERFACE
SDNS010C – JANUARY 1994 – REVISED OCTOBER 1995
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
SBus Device That Provides Asynchronous
Transfer-Mode Interface
Single-Chip Segmentation and Reassembly
(SAR) for Full-Duplex ATM Adaptation-
Layer (AAL) Processing
On-Chip SBus Host Interface Allows Use of
Host Memory for Packet SAR
53-Byte ATM Cells Are Transparent to the
User
Provides Complete Encapsulation and
Termination of AAL5 and Limited AAL3/4
Features a Null AAL That Provides
Functions for Constant-Bit-Rate Services
Supports 1023 Unique Virtual Circuits
(VCs) on Receive Side
Explicit Cell-Level Interleaving Between
Groups of VCs
Packet Interface Is Managed by Efficient
Descriptor Rings
Physical (PHY)-Layer Interface Is Full
Duplex
Supports PHY-Layer Data Rates in the
Range of 25.6 Mbit/s to 155.52 Mbit/s
Interfaces Directly to the TNETA1500
SONET ATM BiCMOS Receiver/Transmitter
(SABRE)
Recognizes ATM-Layer Operation and
Maintenance (OAM) Cells
No External Logic Required for Host Bus to
Ensure Simple Design
description
The TNETA1560 is an asynchronous transfer mode (ATM) segmentation and reassembly (SAR) device with
an SBus interface. This device incorporates ATM adaptation-layer (AAL) processing, ATM SAR processing for
full-duplex operation up to the STS-3c rate of 155.52 Mbit/s, and the controls for the register interface on the
physical (PHY) layer. The device provides a packet interface that is managed by descriptor rings, making the
53-byte ATM-framing format transparent to the user. The device passes the payload of 48 bytes, constituting
the payload of each cell, across the SBus-host interface. All packets are segmented and reassembled in host
memory and accessed by the chip via the descriptor-ring mechanism. This operation reduces the memory
requirements for network-interface cards (NICs). The TNETA1560 requires no local processor on the card,
which enables very compact solutions.
The applications for the TNETA1560 include NICs for client workstations and servers, embedded applications
like LAN emulation, and multiprotocol systems like video servers. The TNETA1560 provides complete AAL5
encapsulation and termination in hardware. In addition, limited support is provided for AAL3/4 and a null AAL
is provided to facilitate real-time data transfer. The TNETA1560 recognizes ATM-layer operation and
maintenance (OAM) cells.
In the transmit direction, the TNETA1560 generates data via a special bit-rate control table that provides explicit
cell-level interleaving between groups of virtual circuits (VCs). This mechanism brings a higher degree of
flexibility when specifying peak rates for each group (up to 155.52 Mbit/s at a resolution greater than 32 kbit/s).
The VCs within a group are serviced via a first-in, first-out (FIFO) discipline on a per-packet basis.
In the receive direction, the TNETA1560 allows multiple virtual paths (VPs) with the condition that each VC is
unique. The device is primarily intended for AAL5 encapsulation and termination that is supported in hardware.
The TNETA1560 has four interfaces that include: the SBus interface with a 32-bit-wide data bus, the cell
interface, a control-memory interface to access the local SRAM, and the local-bus interface to access the
PHY-layer register and an EPROM. The cell interface to the PHY layer consists of an 8-bit-wide data path and
associated control signals in both the transmit and receive directions. The 53-byte ATM cells pass between the
ATM and PHY layers.
Copyright
1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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