參數(shù)資料
型號(hào)： TNETA1560
廠商： Texas Instruments, Inc.
英文描述： ATM Segmentation and Reassembly Device with SBUS Host Interface(ATM 分段和重設(shè)裝置帶SBUS主機(jī)接口)
中文描述： 自動(dòng)柜員機(jī)分段和重組與SBus主機(jī)接口（自動(dòng)柜員機(jī)分段和重設(shè)裝置帶SBU的主機(jī)接口設(shè)備）
文件頁(yè)數(shù)： 27/40頁(yè)
文件大?。?/td> 804K
代理商： TNETA1560
TNETA1560
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH SBUS HOST INTERFACE
SDNS010C – JANUARY 1994 – REVISED OCTOBER 1995
27
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
transmit data-descriptor rings
Each of the 255 transmit data-descriptor rings holds 256 entries and each ring represents one transmit packet
queued for transmission. A packet is composed of one or more transmit buffers. The host posts entries to the
rings and the SAR processes each entry within the given ring. Table 6 shows the composition of the four-word
entry.
Table 6. Transmit-Data Descriptor-Ring Summary
ENTRY
DESCRIPTION
Word 0
Control field, packet length, buffer length
Word 1
Start-of-buffer pointer – 32 bits
Word 2
4-byte ATM header
Word 3
AAL5 tail – control and length fields
TX descriptor-ring word 0 – configuration
Control (bits 31 – 27)
Packet length (bits 26 – 16)
Buffer length (bits 15 – 0)
OWN (bit 31)
The descriptor is owned by the SBus SAR when the OWN bit is set. The descriptor is owned by the host when
the OWN bit is zero. The OWN bit is set by the host when a buffer/packet is queued for transmission. When
the next BWG index from the BWG table does not have an active buffer location in the transmit DMA entry, the
SBus SAR attempts to recover a new buffer-descriptor entry from the transmit data-descriptor ring. This entry
is loaded into the DMA entry if the OWN bit is set. If the OWN bit for the first descriptor in the transmit
data-descriptor ring is zero, no data is queued for transmission and an idle cell is transmitted.
The host places all the buffers for a packet in the descriptor ring before setting the OWN bits on the entries
representing each buffer in sequence from the last buffer to the first buffer (in reverse order). The SBus SAR
clears the OWN bit after if finishes transmitting/processing the bytes associated with the buffer pointed to by
the DMA entry. When the OWN bit is cleared by the host, word 0 is not meaningful and is overwritten by the host.
start of chain (SOC) (bit 30)
The SOC bit indicates that this is the first buffer of a packet, which consists of one or more buffers. This bit is
also set in packets with single buffers.
end of chain (EOC) (bit 29)
The EOC bit indicates that this is the last buffer of a packet. Single buffer packets have both the SOC and EOC
bits set. Packets with multiple buffers have the SOC bit set on the first buffer and the EOC bit set on the last
buffer.
AAL type – AAL5 indicator (bit 27)
The AAL-type bit indicates the packet/buffer described in this descriptor-ring entry is an AAL5 packet. When
zero, this bit indicates to the SAR that AAL5 processing should be performed in the transmit direction. This
includes addition of the pad, the control- and packet-length fields, and the 32-bit CRC. The total size of the AAL5
packet is a multiple of 48 bytes.
The SBus SAR does not perform any packet-level encapsulation similar to that used in AAL5 for either AAL3/4
or the null AAL. The host provides packets correctly formatted into 48-byte cells to the SAR.
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