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| 型號(hào)： | TNETA1560 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | ATM Segmentation and Reassembly Device with SBUS Host Interface(ATM 分段和重設(shè)裝置帶SBUS主機(jī)接口) |
| 中文描述： | 自動(dòng)柜員機(jī)分段和重組與SBus主機(jī)接口（自動(dòng)柜員機(jī)分段和重設(shè)裝置帶SBU的主機(jī)接口設(shè)備） |
| 文件頁(yè)數(shù)： | 25/40頁(yè) |
| 文件大?。?/td> | 804K |
| 代理商： | TNETA1560 |
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TNETA1560
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH SBUS HOST INTERFACE
SDNS010C – JANUARY 1994 – REVISED OCTOBER 1995
25
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
data management (continued)
TX Descriptor Rings
(255 rings,
each ring: 256 entries)
BWG Table
(max 4800 entries)
Data Buffers
(48-byte cell payload)
VCI DMA States
(1024 states)
Small Free-Buffer Ring
(256 entries)
Big Free-Buffer Ring
(256 entries)
RX Completion Ring
(256 entries)
BWG DMA States
(255 states)
TX Completion Ring
(256 entries)
Data Buffers
(48-byte cell payload)
Transmit
Receive
SAR-
Control
Memory
Host
Memory
Figure 15. SBus SAR Data Organization
Several registers stored in the control memory indicate the address of the next entry in the two free-buffer rings
and the two completion rings. The descriptor rings apply to packet- or buffer-level processing, whereas the DMA
channels apply to per-cell processing. The transmit DMA state for each BWG indicates the location of each
transmit descriptor ring.
programmer’s reference
This section presents the SBus SAR data structures in detail. The contents of various physical locations are
summarized in Table 3. A large part of this information is presented in Figure 15 but is duplicated here for
convenience.
Table 3. Location of SBus SAR Data Structures
CONTROL
MEMORY
BWG table
HOST
MEMORY
SAR
REGISTERS
EPROM
TX descriptor rings (255)
Configuration registers
Boot code
TX DMA states
TX completion ring
Operation registers
48-bit address
RX DMA states
Small free-buffer ring
Diagnostics
Initialization block
Big free-buffer ring
SBus ID
RX completion ring
Data buffers
The system has a bus width of four bytes and all transactions are conducted on 4-byte boundaries. The SBus
SAR uses big-endian addressing by definition as an SBus device. All addresses are in hexadecimal notation
unless otherwise specified.
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