參數(shù)資料
型號(hào)： TNETA1560
廠商： Texas Instruments, Inc.
英文描述： ATM Segmentation and Reassembly Device with SBUS Host Interface(ATM 分段和重設(shè)裝置帶SBUS主機(jī)接口)
中文描述： 自動(dòng)柜員機(jī)分段和重組與SBus主機(jī)接口（自動(dòng)柜員機(jī)分段和重設(shè)裝置帶SBU的主機(jī)接口設(shè)備）
文件頁(yè)數(shù)： 23/40頁(yè)
文件大小： 804K
代理商： TNETA1560
TNETA1560
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH SBUS HOST INTERFACE
SDNS010C – JANUARY 1994 – REVISED OCTOBER 1995
23
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
local-bus interface
Since there could be several devices on the local bus, the SBus SAR accepts a ready signal from devices on
the bus as a handshake. The bus transaction is assumed to be complete eight SBus cycles (at least 320 ns)
after the transaction is initiated, regardless of the ready signal. This accommodates slow devices such as
EPROMs and also can be used to relax timing constraints on the register interface for the PHY-layer devices.
The local bus is accessed exclusively via SBus transactions with the SAR as the slave with the exception of the
local-bus interrupt signal. The lower 16 bits of the SBus address bus are directly routed to the local-bus (LBus)
address bus. The SBus address must remain stable while the local bus is active. This is achieved by not
returning an acknowledgment signal on SBus until the LBus transaction is complete.
architecture
Figure 14 depicts a data-flow representation of the SBus SAR architecture.
To
Control Memory
RAM
Local
Bus
SBus
PHY
Data
Interface
S
XBTP
XALP
XMB
XPIN
C
A
Control-Memory Interface
and Arbitration
(CMIA)
RBTP
RALP
RCB
RPIN
LBIN
User
Register
Transmit Modules
Receive Modules
Figure 14. SBus SAR Architecture
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