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| 型號： | SMJ34020AHT |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | GRAPHICS SYSTEM PROCESSOR |
| 中文描述： | 圖形系統(tǒng)處理器 |
| 文件頁數(shù)： | 79/92頁 |
| 文件大?。?/td> | 1458K |
| 代理商： | SMJ34020AHT |
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SMJ34020A
GRAPHICS SYSTEMPROCESSOR
SGUS011B – APRIL 1991 – REVISED AUGUST 1995
79
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
local-bus timing: RAS, CAS0–CAS3, WE, TR/QE, and SF (see Notes 4 and 8 and Figure 42)
NO.
’34020A-32
MIN
’34020A-40
MIN
UNIT
MAX
MAX
62
th(LAV-CTV)
Hold time, LAD0–LAD31 read data valid
after earlier of DDIN, low after RAS,
CAS, or TR/QE high
3.5
3.5
ns
76
td(CK1L-REL)
Delay time, RAS low after LCLK1 no
longer high
tQ+12+s
tQ+10+ s
ns
77
td(CK1L-REH)
Delay time, RAS high after LCLK1 no
longer high
tQ+12
tQ+10
ns
78
td(CK1H-CEL)
Delay time, CAS low after LCLK1 no
longer low
tQ+12
tQ+10
ns
79
td(CK1L-CEH)
Delay time, CAS high after LCLK1 no
longer high
tQ+12
tQ+10
ns
80
td(CK2L-WEL)
Delay time, WE low after LCLK2 no
longer high
tQ+15+s
tQ+13.5+ s
ns
81
td(CK1L-WEH)
Delay time, WE high after LCLK1 no
longer high
tQ+15
tQ + 15
ns
82
td(CK2L-TRL)
Delay time, TR/QE low after LCLK2 no
longer high
tQ+15+s
tQ+13.5+ s
ns
83
td(CK1L-TRH)
Delay time, TR/QE high after LCLK1 no
longer high
tQ+15
tQ+13.5
ns
84
td(CK1H-SFV)
Delay time, SF valid after LCLK1 no
longer low
tQ+22
tQ+20
ns
85
td(CK2L-SFV)
Delay time, SF valid after LCLK2 no
longer high
tQ+22+s
tQ+20+ s
ns
86
td(CK2L-SFZ)
Delay time, SF in the high-impedance
state after LCLK2 no longer high
tQ+22
tQ+20
ns
87
tsu(ADV-REL)
Setup time, row address valid before
RAS no longer high
2tQ–22
2tQ– 20
ns
88
th(ADV-REL)
Hold time, row address valid after RAS
low
tQ–5+ s
tQ– 5+ s
ns
89
tsu(RCV-CEL)
Setup time, column address valid before
CAS no longer high
tQ–22
tQ– 20
ns
90
th(RCV-CEH)
Hold time, column address valid after
CAS high
tQ–15
tQ– 13.5
ns
91
tsu(CAV-CEL)
Setup time, write data valid before CAS
no longer high
tQ–22
tQ– 20
ns
92
th(CAV-CEH)
Hold time, write data valid after CAS no
longer low
tQ–15
tQ– 13.5
ns
93
ta(LAV-REL)
Access time, data-in valid after RAS low
(assuming maximum transition time)
4tQ–8+s
4tQ– 8+ s
ns
94
ta(LAV-CEL)
Access time, data-in valid after CASL no
longer high
2tQ–8+s
2tQ–8+s
ns
95
ta(LAV-RCV)
Access time, data-in valid after column
address valid
3tQ–20+s
3tQ – 12
ns
These values are derived from characterization data and are not tested.
Parameters 87 and 88 also apply to WE, TR/QE, and SF relative to RAS.
NOTES:
4. s= tQ if using the clock stretch;
s= 0 otherwise
8. Parameter 96 has been eliminated.
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