參數(shù)資料
型號(hào)： SMJ34020AHT
廠商： Texas Instruments, Inc.
英文描述： GRAPHICS SYSTEM PROCESSOR
中文描述： 圖形系統(tǒng)處理器
文件頁(yè)數(shù)： 44/92頁(yè)
文件大小： 1458K
代理商： SMJ34020AHT
SMJ34020A
GRAPHICS SYSTEMPROCESSOR
SGUS011B – APRIL 1991 – REVISED AUGUST 1995
44
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
cycle timing examples (continued)
In Figure 18, transition points are shown for R0 and R1 to indicate where they occur relative to the other signals.
This example indicates that the SMJ34020A has control of the bus, yields control, and then regains control. The
SMJ34020A regains bus mastership as soon as GI is driven active (low). R0 and R1 could be outputting any
of the codes with the exception of the access-termination code. The bus arbitration logic must control the timing
of GI to all of the processors requiring the bus.
It is recommended that SMJ34020A clock stretch not be used in multiprocessor systems.
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