參數(shù)資料
型號(hào): SMJ44400
廠商: Electronic Theatre Controls, Inc.
英文描述: 1M x 4 DRAM DYNAMIC RANDOM-ACCESS MEMORY
中文描述: 100萬× 4的DRAM動(dòng)態(tài)隨機(jī)存取存儲(chǔ)器
文件頁數(shù): 1/21頁
文件大?。?/td> 351K
代理商: SMJ44400
DRAM
SMJ44400
Austin Semiconductor, Inc.
SMJ44400
Rev. 2.0 10/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
FEATURES
Organized 1,048,576 x 4
Single +5V ±10% power supply
Enhanced Page-Mode operation for faster memory access
P
Higher data bandwidth than conventional page-mode
parts
P
Random Single-Bit Access within a row with a column
address
CAS\-Before-RAS\ (CBR) Refresh
Long Refresh period: 1024-cycle Refresh in 16ms (Max)
3-State unlatched Output
Low Power Dissipation
All Inputs/Outputs and Clocks are TTL Compatible
Processing to MIL-STD-883, Class B available
OPTIONS
Timing
80ns access
100ns access
120ns access
MARKING
-80
-10
-12
Package(s)
Ceramic DIP (400mils)
Ceramic Flatpack
JD
HR
No. 113
No. 308
Operating Temperature Ranges
Military (-55
o
C to +125
o
C)
M
PIN ASSIGNMENT
(Top View)
AVAILABLE AS MILITARY
SPECIFICATIONS
SMD 5962-90847
MIL-STD-883
20-Pin DIP (JD)
20-Pin Flatpack (HR)
(400 MIL)
GENERAL DESCRIPTION
The SMJ44400 is a series of 4,194,304-bit dynamic ran-
dom-access memories (DRAMs), organized as 1,048,576
words of four bits each. This series employs state-of-the-art
technology for high performance, reliability, and low-power
operation.
The SMJ44400 features maximum row access times of
80ns, 100ns, and 120ns. Maximum power dissipation is as
low as 360mW operating and 22mW standby.
All inputs and outputs, including clocks, are compatible
with Series 54 TTL. All addressses and data-in lines are latched
on-chip to simplify system design. Data out is unlatched to
allow greater system flexibility.
1M x 4 DRAM
DYNAMIC RANDOM-ACCESS
MEMORY
For more products and information
please visit our web site at
www.austinsemiconductor.com
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20
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DQ1
DQ2
W\
RAS\
A9
A0
A1
A2
A3
Vcc
Vss
DQ4
DQ3
CAS\
OE\
A8
A7
A6
A5
A4
The SMJ44400 is offered in a 400-mil, 20-pin ceramic
side-brazed dual-in-line package (JD suffix) and a 20-pin
ceramic flatpack (HR suffix) that are characterized for
operation from -55°C to +125°C.
OPERATION
Enhanced Page Mode
Enhanced page-mode operation allows faster memory
access by keeping the same row address while selecting
random column addresses. The time for row-address setup
and hold and address multiplex is eliminated. The maximum
number of columns that can be accessed is determined by the
maximum RAS\ low time and the CAS\ page cycle time used.
With minimum CAS\ page cycle time, all 1024 columns
specified by column addresses A0 through A9 can be accessed
without intervening RAS\ cycles.
Unlike conventional page-mode DRAMs, the column-
address buffers in this device are activated on the
Pin Name
A0 - A9
CAS\
DQ1 - DQ4 Data Inputs/Outputs
OE\
Output Enable
RAS\
Row-Address Strobe
W\
Write Enable
Vcc
5V Supply
Vss
Ground
Function
Address Inputs
Column-Address Strobe
相關(guān)PDF資料
PDF描述
SMJ44400HR 1M x 4 DRAM DYNAMIC RANDOM-ACCESS MEMORY
SMJ44400JD 1M x 4 DRAM DYNAMIC RANDOM-ACCESS MEMORY
SMJ44C251B 262144 BY 4-BIT MULTIPORT VIDEO RAM
SMJ4C1024-10HJ 1048576 BY 1-BIT DYNAMIC RANDOM-ACCESS MEMORY
SMJ4C1024-10HK 1048576 BY 1-BIT DYNAMIC RANDOM-ACCESS MEMORY
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SMJ44400JD 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1M x 4 DRAM DYNAMIC RANDOM-ACCESS MEMORY