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SMJ34020A
GRAPHICS SYSTEMPROCESSOR
SGUS011B – APRIL 1991 – REVISED AUGUST 1995
63
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
DC electrical characteristics over recommended range of supply voltage (see Note 3)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BUSFLT, LRDY, VCLK,
PGMD SIZE16 CSYNC
PGMD, SIZE16, CSYNC,
VSYNC, HSYNC
GB PKG
2.2
VCC+0.3
HT PKG
2.3
VCC+0.3
VCC+0.3
VCC+0.3
VCC+0.3
VCC+0.3
VCC+0.3
VCC+0.3
0.8
HWRITE HREAD
HWRITE, HREAD
GB PKG
2
VIH
High-level input
voltage
HT PKG
2.3
V
HA5–HA31, HCS,
HBS0–HBS3
GB PKG
2
HT PKG
2.3
CLKIN only
3
All other inputs
2
VIL
Low-level input voltage, HT only: HCS VIL = – 0.3 min, 0.7 V max
–0.3
V
VOH
High-level output voltage
VCC = MIN,
IOH = MAX
2.6
V
GB PKG
0.60
VOL
Low-level output
voltage
DDIN, HINT, HRDY, R0, R1,
EMU3
HT PKG
VCC = MAX,
IOL= MIN
IOL = MIN
0.8
V
HYSNC, VSYNC
0.8
All other outputs
0.6
GB PKG
VCC = MAX,
VO = 2.8 V
20
IO
Output current leakage (high impedance)
Output current, leakage (high impedance)
HT PKG
20
μ
A
GB PKG
VCC = MAX,
VO = 0.6 V
– 20
HT PKG
–20
II
Input current (All inputs except EMU0–EMU2,
HREAD, HWRITE)
VI = VSS to VCC
±
20
μ
A
ICC
Supply current
’34020A-32
VCC = MAX,
Freq = MAX
265
mA
’34020A-40
280
Ci
Co
All typical values are at VCC = 5 V, TA = 25
°
C.
EMU0–EMU2 are not connected in a typical configuration. Nominal pullup current for EMU0–EMU2 and HREAD, HWRITE is 600
μ
A.
NOTE 3: HDST and HOE (output terminals) have internal pullup resistors that allow high logic levels to be maintained when the SMJ34020A is
not actually driving these pins.
Input capacitance
10
18
pF
Output capacitance
18
25
pF
signal transition levels
2 V
(see Note A)
0.8 V
NOTE A: 2.2 V for BUSFLT, VCLK, LRDY, PGMD, SIZE16. 3V for CLKIN.
Figure 30. TTL-Level Inputs
For high-to-low and low-to-high transitions, the level at which the input timing is measured is 1.5 V.