參數(shù)資料
型號(hào)： SMJ34020AHT
廠商： Texas Instruments, Inc.
英文描述： GRAPHICS SYSTEM PROCESSOR
中文描述： 圖形系統(tǒng)處理器
文件頁數(shù)： 23/92頁
文件大?。?/td> 1458K
代理商： SMJ34020AHT
SMJ34020A
GRAPHICS SYSTEMPROCESSOR
SGUS011B – APRIL 1991 – REVISED AUGUST 1995
23
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
a clock-stretch timing example, SMJ34020A-32 and 150-ns DRAMs
This example analyzes a memory interface timing parameter. It shows that the clock-stretch mechanism can
be used to allow the SMJ34020A-32 to avoid a timing violation when interfaced to 100-ns VRAMs.
Consider a system with:
A SMJ34020A-32,
which has a 32-MHz clock input frequency and hence a 125-ns cycle time, so
t
Q
= 31 ns. Timing parameters are taken from this data sheet.
1 megabit
×
1 bit DRAM. Timing parameters are taken from the corresponding
Texas Instruments data sheet.
A SMJ44C251-10
row address hold data after RAS low, t
h(ADV-REL)
Without clock stretch
SMJ4C1024
SMJ34020A
t
h(RA)
Parameter 88
Hold time, row address valid after RAS low
Hold time, row address valid after RAS low
Min = 20 ns
Min = t
Q
– 5 ns = 26 ns
If RAS is passed through a PAL
with a delay of 7 ns, then t
h(RA)
seen by the DRAM is 26 ns – 7 ns = 19 ns.
This violates the 20 ns minimum.
With clock stretch
SMJ34020A
Parameter 88
t
h(ADV-REL)
Hold time, row address valid after RAS low
Min = 2t
Q
– 5 ns = 57 ns
With the same 7-ns PAL delay, the DRAM sees t
h(RA)
as 57 ns – 7ns = 50 ns, which does not violate the
20 ns minimum.
cycle timing examples
The following figures show examples of many of the basic cycles that the SMJ34020A uses for memory access,
VRAM control, multiprocessor bus control, and coprocessor communication. These figures should not be used
to determine specific signal timings, but can be used to see signal relationships for the various cycles. The
Q4 phases that couldbe stretched are marked with an * on the diagrams. The conditions required for the stretch
are:
The design uses a SMJ34020A.
The CONFIG register’s CSE bit is set to 1.
The SMJ34020A is doing either:
a)
Any address cycle, or
b)
A read data cycle in a read-modify-write sequence
The following remarks apply to memory timing in general. A row address is output on RCA0–RCA12 at the start
of a cycle along with the full address and status on LAD0–LAD31. These remain valid until after the fall of ALTCH
and RAS. The column address is then output on RCA0–RCA12, and LAD0–LAD31 are set to read or write data
for the memory access. During a write, the data and WE are set valid prior to the falling edge of CAS; the data
remains valid until after WE and CAS have returned high.
Large memory configurations can require external buffering of the address and data lines. DDIN and DDOUT
coordinate these external buffers with LAD.
During the address output to LAD by the SMJ34020A (Figure 2), the least significant four bits (LAD0–LAD3)
contain a bus-status code. PGMD low at the start of Q2 after RAS low indicates that this memory supports
page-mode operation. LRDY high at the start of Q2 after RAS low indicates that the cycle can continue without
inserting wait states. DDOUT returns high after the initial address output on LAD (during Q4), indicating that
a memory read cycle is about to take place.
PAL is a trademark of Advanced Micro Devices, Inc.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SMJ34020AHTM32 制造商:TI 制造商全稱:Texas Instruments 功能描述:GRAPHICS SYSTEM PROCESSOR
SMJ34020AHTM40 制造商:TI 制造商全稱:Texas Instruments 功能描述:GRAPHICS SYSTEM PROCESSOR
SMJ34020HTM28 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:
SMJ34061GB 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Non-VGA Video Controller
SMJ34061GBS 制造商:Rochester Electronics LLC 功能描述:- Bulk
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