參數(shù)資料
型號: SMJ34020AHT
廠商: Texas Instruments, Inc.
英文描述: GRAPHICS SYSTEM PROCESSOR
中文描述: 圖形系統(tǒng)處理器
文件頁數(shù): 46/92頁
文件大小: 1458K
代理商: SMJ34020AHT
SMJ34020A
GRAPHICS SYSTEMPROCESSOR
SGUS011B – APRIL 1991 – REVISED AUGUST 1995
46
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
cycle timing examples (continued)
Two SMJ34020As use the multiprocessor interface to pass control of local memory from one to the other
(Figure 19). GSP1 completes a read cycle to the local memory and, although desiring another read, loses the
bus to GSP2, which does a single write cycle (perhaps a host-write access). GSP1 then regains control and
completes the read cycle (shown with a single wait state). Since no further memory-access requests are
present, GSP1 maintains control of the bus and holds all of the local-memory control signals at their inactive
levels. LRDY is a common input to both GSP1 and GSP2.
The host cycle timing diagrams shown in this data sheet are only a sample. For more information, see the
TMS34020 User’s Guide.
1
2
3 4
1
2
3 4
1
2
3 4
1
2
3 4
1
2
3 4
1
2
3 4
1
2
3 4
1
2
3 4
1
1
2
3 4
1
2
3 4
1
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3 4
1
2
3 4
1
2
3 4
1
2
3 4
1
2
3 4
1
2
3 4
1
GSP1 Read
GSP2 Write
GSP1 Read With Wait
Bus Idle
GSP1
GI
R0
R1
RAS
CAS
WE
TR/QE
DDIN
DDOUT
ALTCH
LRDY
ALTCH
GI
R0
R1
RAS
CAS
WE
TR/QE
DDIN
DDOUT
GSP2
Figure 19. Multiprocessor-Interface Cycle Timing (Passing Control)
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