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| 型號： | SMJ34020AHT |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | GRAPHICS SYSTEM PROCESSOR |
| 中文描述： | 圖形系統(tǒng)處理器 |
| 文件頁數(shù)： | 43/92頁 |
| 文件大小： | 1458K |
| 代理商： | SMJ34020AHT |
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SMJ34020A
GRAPHICS SYSTEMPROCESSOR
SGUS011B – APRIL 1991 – REVISED AUGUST 1995
43
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
cycle timing examples (continued)
This VRAM cycle (Figure 17) is performed when a pixel-write instruction is executed with the CST bit in DPYCTL
set. This cycle is indicated by TR/QE and WE low and SF and CAS high at the time RAS goes low. This cycle
does not require the use of SOE of the VRAM and does not affect the status of the serial I/O pins. During the
address portion of the cycle, the status on LAD0–LAD3 indicates that a CPU-initiated VRAM
register-to-memory transfer (status code = 0101) is being performed. Although PGMD and SIZE16 are ignored
on this cycle, they should be held at valid levels as shown.
Q4
Q1
Q2
Q3
Q1
Q2
Q3
Q4
Q1
Row
Address
Tap Point
GI
LAD
CAMD
RCA
ALTCH
RAS
CAS
WE
TR/QE
SF
DDIN
DDOUT
LRDY
PGMD
SIZE16
BUSFLT
R0
R1
Q4
See clock stretch, page 20.
Figure 17. Serial-Data-Register-to-Memory Cycle Timing (VRAM-Alternate-Write Transfer)
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