參數(shù)資料
型號(hào): SMJ34020AHT
廠商: Texas Instruments, Inc.
英文描述: GRAPHICS SYSTEM PROCESSOR
中文描述: 圖形系統(tǒng)處理器
文件頁數(shù): 12/92頁
文件大?。?/td> 1458K
代理商: SMJ34020AHT
SMJ34020A
GRAPHICS SYSTEMPROCESSOR
SGUS011B – APRIL 1991 – REVISED AUGUST 1995
12
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
memory controller/local-memory interface
The memory controller manages the SMJ34020A’s interface to the local memory and automatically performs
the bit alignment and masking necessary to access data located at arbitrary bit boundaries within memory. The
memory controller operates autonomously with respect to the CPU. It has a write queue one field (1 to 32 bits)
deep that permits it to complete those memory cycles necessary to insert a field into memory without delaying
the execution of subsequent instructions. Only when a second memory operation is required before completion
of the first operation is the SMJ34020A forced to defer execution of the subsequent instruction.
The SMJ34020A directly interfaces to standard DRAMs and in particular, to standard video RAMs (VRAMs)
such as the SMJ44C25x multiport VRAMs. The SMJ34020A memory interface consists of the local
address/data bus (LAD), the DRAM row/column address (RCA) bus, and associated control signals. The
currently selected word address (28 bits) and status (4 bits) are multiplexed with data on LAD. The RCA bus
allows direct connection to address/address multiplexed DRAMs from 64K to 16M. Refresh for DRAMs is
supported by CAS-before-RAS (CBR) refresh cycles.
BIT 232 –1
(Last Bit in Memory)
68 Words
226 –66560 Words
(67 042 304 Words)
(3
×
226) –64K
(201 261 056 Words)
444 Words
65024 Words
512 Words
448 Words
64 Words
64K Words
Interrupt Vectors and
Extended Trap Vectors
Reserved for Interrupt Vectors
and Extended Trap Vectors
General Use and
Extended Trap Vectors
General Use and Extended
Trap Vectors
Bit 0
(First Bit in Memory)
General Use
Reserved for System I/O
Reserved for I/O Registers
I/O Registers
General Use
ADDRESS
FFFFFFF0h
FFFFFBC0h
FFFFFBB0h
FFFFE000h
FFFFDFF0h
FFFF0000h
FFEFFFF0h
C0004000h
C0003FF0h
C0002000h
C0001FF0h
C0000400h
C00003F0h
C0000000h
BFFFFFF0h
00100000h
000FFFF0h
00000000h
16
Figure 1. Memory Map
相關(guān)PDF資料
PDF描述
SMJ4256 262,144-BIT DYNAMIC RANDOM-ACCESS MEMORY
SMJ4256FV 262,144-BIT DYNAMIC RANDOM-ACCESS MEMORY
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SMJ44400 1M x 4 DRAM DYNAMIC RANDOM-ACCESS MEMORY
SMJ44400HR 1M x 4 DRAM DYNAMIC RANDOM-ACCESS MEMORY
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