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參數(shù)資料
| 型號(hào)： | SMJ34020AHT |
| 廠(chǎng)商： | Texas Instruments, Inc. |
| 英文描述： | GRAPHICS SYSTEM PROCESSOR |
| 中文描述： | 圖形系統(tǒng)處理器 |
| 文件頁(yè)數(shù)： | 35/92頁(yè) |
| 文件大小： | 1458K |
| 代理商： | SMJ34020AHT |
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SMJ34020A
GRAPHICS SYSTEMPROCESSOR
SGUS011B – APRIL 1991 – REVISED AUGUST 1995
35
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
cycle timing examples (continued)
The clock stretch is generated by the VLCOL instruction and is indicated by CAS, WE, TR/QE, and SF high
at the falling edge of RAS and SF high at the falling edge of CAS (Figure 10). The data in the COLOR1 register
is output on LAD to be written to a special register on the VRAM that is used in subsequent cycles requiring a
color latch. During the address portion of the cycle, the status on LAD0–LAD3 indicates a color-mask load is
being performed (status code = 0111). Although CAMD, PGMD, and SIZE16 are ignored on this cycle, they
should be held at valid levels as shown.
Q4
Q1
Q2
Q3
Q1
Q2
Q3
Q4
Q1
All-Zero Address
Zero Address
Color Register Data
GI
LAD
CAMD
RCA
ALTCH
RAS
CAS
WE
TR/QE
SF
DDIN
DDOUT
LRDY
PGMD
SIZE16
BUSFLT
R0
R1
Q4
See clock stretch, page 20.
Figure 10. Load-Color-Latch-Cycle Timing
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