參數(shù)資料
型號: SMJ34020AHT
廠商: Texas Instruments, Inc.
英文描述: GRAPHICS SYSTEM PROCESSOR
中文描述: 圖形系統(tǒng)處理器
文件頁數(shù): 73/92頁
文件大小: 1458K
代理商: SMJ34020AHT
SMJ34020A
GRAPHICS SYSTEMPROCESSOR
SGUS011B – APRIL 1991 – REVISED AUGUST 1995
73
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
host-interface-cycle timing responses (random read cycle) (see Note 4 and Figure 37)
NO.
’34020A-30
MIN
’34020A-40
MIN
UNIT
MAX
MAX
26
tw(RDH)
Pulse duration, HREAD high
28
25
ns
33
tsu(RDL-CK2L)
Setup time, HCS low or HREAD low to LCLK2 no
longer high
30
25
ns
39
td(CK1H-RYH)
Delay time, LCLK1 going high to HRDY high (end of
read cycle)
tQ+20
tQ+18
ns
40
td(RDH-RYL)
td(CK2L-STL)
td(CK1L-STH)
tsu(STL-RYH)
td(RYH-STH)
Delay time, HREAD or HCS high to HRDY low
20
18
ns
41
Delay time, LCLK2 no longer high to HDST low
s+
tQ+15
tQ+15
tQ+13.5+s
tQ–13.5
2tQ+13.5
2tQ+13.5
ns
42
Delay time, LCLK1 no longer high to HDST high
ns
43
Setup time, HDST low to HRDY no longer low
tQ–15
ns
44
Delay time, HRDY no longer low to HDST high
2tQ+15
ns
Setup time to ensure recognition of input on this clock edge.
NOTE 4: s= tQ if using the clock stretch;
s= 0 otherwise
.
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
LCLK1
LCLK2
HCS/HREAD
HRDY
HDST
33
43
33
26
40
41
39
42
44
See clock stretch, page 20.
Figure 37. Host-Interface-Cycle Timing Responses (Random Read Cycle)
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