參數(shù)資料
型號(hào)： SMJ34020AHT
廠商： Texas Instruments, Inc.
英文描述： GRAPHICS SYSTEM PROCESSOR
中文描述： 圖形系統(tǒng)處理器
文件頁(yè)數(shù)： 74/92頁(yè)
文件大?。?/td> 1458K
代理商： SMJ34020AHT
SMJ34020A
GRAPHICS SYSTEMPROCESSOR
SGUS011B – APRIL 1991 – REVISED AUGUST 1995
74
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
host-interface-cycle timing (block-read cycle) (see Notes 4 and 6 and Figure 38)
NO.
’34020A-32
MIN
’34020A-40
MIN
UNIT
MAX
MAX
26
tw(RDH)
tw(RDL)
Pulse duration, HREAD high
28
25
ns
30
Pulse duration, HREAD low
18
15
ns
37
tsu(RDH-CK2L)
Setup time, HREAD high to LCLK2 no longer high,
prefetch read mode
30
25
ns
39
td(CK1H-RYH)
td(RDH-RYL)
td(CK2L-STL)
td(CK1L-STH)
tsu(STL-RYH)
td(RYH-STH)
Delay time, LCLK1 no longer low to HRDY high
tQ+20
20
tQ+18
ns
40
Delay time, HREAD or HCS high to HRDY low
18
ns
41
Delay time, LCLK2 no longer high to HDST low
tQ+15+s
tQ+15
tQ+13.5+ s
tQ+13.5
ns
42
Delay time, LCLK1 no longer high to HDST high
ns
43
Setup time, HDST low to HRDY no longer low
tQ–15
tQ–13.5
ns
44
Delay time, HRDY no longer low to HDST high
2tQ+15
2tQ+13.5
ns
45
td(RDL-RYH)
Delay time, HREAD or HCS low to HRDY high after
prefetch
25
20
ns
50
th(STH-CTV)
Hold time, CAS, TR/QE, DDIN valid after HDST high
– 2
– 2
ns
Setup time to ensure recognition of input on this clock edge. When the SMJ34020A is set for block reads, the deassertion of HREAD is used
to request a local memory cycle at the next sequential address location.
NOTES:
4. s= tQ if using the clock stretch;
s= 0 otherwise
6. Although HCS, HREAD, and HWRITE can be totally asynchronous to the SMJ34020A, cycle responses to the signals are
determined by local memory cycles.
HDST
HRDY
HREAD
HCS
LCLK2
LCLK1
43
40
37
42
26
39
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
45
41
44
40
26
37
30
See clock stretch, page 20.
CAS
TR/QE
DDIN
50
Figure 38. Host-Interface-Cycle Timing (Block-Read Cycle)
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