參數(shù)資料
型號： SiI0680ACLU144
廠商： Silicon Image, Inc.
英文描述： PCI to IDE/ATA
中文描述： PCI到IDE / ATA的
文件頁數(shù)： 92/124頁
文件大?。?/td> 820K
代理商： SII0680ACLU144
SiI0680A PCI to IDE/ATA
Data Sheet
9.7.36
IDE0 UDMA Timing
Address Offset: AC
H
Access Type: Read/Write
Reset Value: 0x4009_4009
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0069-C
92
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
D
D
D
D
D
H
R
Device 1 Cycle Time
Count
D
D
D
D
D
H
R
Device 0 Cycle Time
Count
This register defines the UDMA timing register for IDE Channel #0 in the SiI 0680A. See chapter 11 for details on
programming this timing register. The register bits are defined below.
Bit [31:30]
: Device 1 Data Input Delay (R/W) – IDE0 Device 1 Data Input Delay for UDMA Mode. This bit field is
used for programming the data input delay in increments of 2 nsec in UDMA mode.
Bit [29:28]
: Device 1 DSTROBE Delay (R/W) – IDE0 Device 1 DSTROBE Delay for UDMA Mode. This bit field
is used for programming the DSTROBE output delay in increments of 2 nsec in UDMA mode.
Bit [27:25]
: Device 1 HSTROBE Delay (R/W) – IDE0 Device 1 HSTROBE Delay for UDMA Mode. This bit field
is used for programming the HSTROBE output delay in increments of 2 nsec in UDMA mode.
Bit [24:23]
: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [22]
: Reserved (R/W) – This bit field is reserved.
Bit [21:16]
: Device 1 Cycle Time Count (R/W) – IDE0 Device 1 UDMA Cycle Time Count. This bit field is used
for programming the UDMA Active and Recovery Time.
Bit [15:14]
: Device 0 Data Input Delay (R/W) – IDE0 Device 0 Data Input Delay for UDMA Mode. This bit field is
used for programming the data input delay in increments of 2 nsec in UDMA mode.
Bit [13:12]
: Device 0 DSTROBE Delay (R/W) – IDE0 Device 0 DSTROBE Delay for UDMA Mode. This bit field
is used for programming the DSTROBE output delay in increments of 2 nsec in UDMA mode
Bit [11:09]
: Device 0 HSTROBE Delay (R/W) – IDE0 Device 0 HSTROBE Delay for UDMA Mode. This bit field
is used for programming the HSTROBE output delay in increments of 2 nsec in UDMA mode.
Bit [08:07]
: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [06]
: Reserved (R/W) – This bit field is reserved.
Bit [05:00]
: Device 0 Cycle Time Count (R/W) – IDE0 Device 0 UDMA Cycle Time Count. This bit field is used
for programming the UDMA Active and Recovery Time
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