參數(shù)資料
型號(hào)： SiI0680ACLU144
廠商： Silicon Image, Inc.
英文描述： PCI to IDE/ATA
中文描述： PCI到IDE / ATA的
文件頁數(shù)： 26/124頁
文件大?。?/td> 820K
代理商： SII0680ACLU144
SiI0680A PCI to IDE/ATA
Data Sheet
absence of an ATA/ATAPI device at power-up. It is recommended that a 10k
pull-down resistor is recommended to be
connected to this pin.
IDE1 Chip Select
Pin Names: IDE1_CS0_N; IDE1_CS1_N
Pin Numbers: 64, 65
These are the chip select signals from the host used to select the Command Block or Control Block registers. When
IDE1_DMACK_N is asserted, IDE1_CS0_N and IDE1_CS1_N shall be negated and transfers shall be 16 bits wide.
IDE1 Disk Address
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0069-C
26
Pin Names: IDE1_DA[2..0]
Pin Numbers: 68, 67, 66
Disk Address bits 0 through 2 are normally outputs to the ATA connector to select the register in the drive’s Command Block
register. IDE1_DA [2:0] sends address signals to the secondary channel. These address signals are decoded from the
PCI_AD[2:0] and PCI_CBE[3:0] inputs.
IDE1 Disk I/O Read
Pin Name: IDE1_DIOR_N
Pin Number: 69
This is an active low output which enables data to be read from the drive. The duration and repetition rate of IDE1_DIOR_N
cycles is determined by programming the SiI 0680A PIO timing registers. IDE1_DIOR_N to the secondary channel is driven
high when inactive. This signal is defined as HSTROBE in Ultra DMA write mode to write data to the secondary channel drive.
This signal is also defined as secondary channel HDMARDY_N in Ultra DMA read mode.
IDE1 Disk I/O Write
Pin Name: IDE1_DIOW_N
Pin Number: 70
This is an active low output that enables data to be written to the drive. The duration and repetition rate of IDE1_DIOW_N
cycles is determined by programming the SiI 0680A PIO timing registers. IDE1_DIOW_N to the Secondary channel is driven
high when inactive. This signal is also defined as secondary channel STOP in Ultra DMA mode.
IDE1 Cable Detect
Pin Names: IDE1_CBLID_N
Pin Number: 71
IDE1_CBLID_N (Cable Detect) determines the type of cable attached to the primary channel. In general, a low on this pin
indicates that a 40 conductor cable is attached. A high indicates that an 80 conductor cable is attached. Refer to the
ATA/ATAPI-6 Specification for complete details.
IDE1 DMA Acknowledge
Pin Name: IDE1_DMACK_N
Pin Number: 74
This signal is normally used by the SiI 0680A in response to IDE1_DMARQ to either acknowledge that the secondary channel
is ready to accept data, or that data is available. This signal is also used to write CRC code to the secondary channel drive at
the end of each Ultra DMA burst transfer.
IDE1 Interrupt Request
Pin Name: IDE1_INTRQ
Pin Number: 75
Primary channel interrupt request is an input signal used to generate the PCI_INTA_N output. This input should have a 10k
pull-down resistor connected to it.
IDE1 I/O Ready
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