參數(shù)資料
型號(hào)： SiI0680ACLU144
廠商： Silicon Image, Inc.
英文描述： PCI to IDE/ATA
中文描述： PCI到IDE / ATA的
文件頁數(shù)： 61/124頁
文件大?。?/td> 820K
代理商： SII0680ACLU144
Silicon Image, Inc.
9.1.35
IDE1 Task File Timing + Configuration + Status
Address Offset: B0
H
Access Type: Read/Write
Reset Value: 0x6515_0100
SiI0680A PCI to IDE/ATA
Data Sheet
2006 Silicon Image, Inc.
SiI-DS-0069-C
61
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Addr Setup
Count
Active Count
Recovery Count
R
W
W
W
I
V
I
Reserved
C
C
B
C
This register defines the task file timing register for IDE Channel #1 in the SiI 0680A. The register bits are also mapped to
Base Address 5, Offset E0
H
. See Section 9.7.47 for bit definitions.
9.1.36
IDE1 PIO Timing
Address Offset: B4
H
Access Type: Read/Write
Reset Value: 0x62DD_62DD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Device 1 Addr
Setup Count
Device 1 Active Count
Device 1 Recovery
Count
Device 0 Addr
Setup Count
Device 0 Active Count
Device 0 Recovery
Count
This register defines the PIO timing register for IDE Channel #1 in the SiI 0680A. The register bits are also mapped to
Base Address 5, Offset E4
H
. See Section 9.7.48 for bit definitions.
9.1.37
IDE1 DMA Timing
Address Offset: B8
H
Access Type: Read/Write
Reset Value: 0x4392_4392
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Device 1 Addr
Setup Count
Device 1 Active Count
Device 1 Recovery
Count
Device 0 Addr
Setup Count
Device 0 Active Count
Device 0 Recovery
Count
This register defines the DMA timing register for IDE Channel #1 in the SiI 0680A. The register bits are also mapped to
Base Address 5, Offset E8
H
. See Section 9.7.48 for bit definitions.
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