- 您現在的位置：買賣IC網 > PDF目錄365565 > SiI0680ACLU144 (Silicon Image, Inc.) PCI to IDE/ATA PDF資料下載
參數資料
| 型號： | SiI0680ACLU144 |
| 廠商： | Silicon Image, Inc. |
| 英文描述： | PCI to IDE/ATA |
| 中文描述： | PCI到IDE / ATA的 |
| 文件頁數： | 89/124頁 |
| 文件大小： | 820K |
| 代理商： | SII0680ACLU144 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁當前第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁
Silicon Image, Inc.
SiI0680A PCI to IDE/ATA
Data Sheet
2006 Silicon Image, Inc.
SiI-DS-0069-C
89
9.7.33
Address Offset: A0
H
Access Type: Read/Write
Reset Value: 0x6515_0100
IDE0 Task File Timing + Configuration + Status
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Addr Setup
Count
Active Count
Recovery Count
R
W
W
W
I
V
I
R
Reserved
C
C
B
C
This register defines the task file timing register for IDE Channel #0 in the SiI 0680A. The register bits are defined below.
Bit [31:28]
: Addr Setup Count (R/W) – IDE0 Address Setup Time Count. This bit field is used for adjusting the
address setup time relative to IDE0_DIOR_N and IDE0_DIOW_N. See Chapter 11 for details on programming
the timing register.
Bit [27:22]
: Active Count (R/W) – IDE0 DIOR_N and DIOW_N Active Time Count. This bit field is used for
adjusting the active time of IDE0_DIOR_N and IDE0_DIOW_N. See Chapter 11 for details on programming this
timing register.
Bit [21:16]
: Recovery Count (R/W) – IDE0 DIOR_N and DIOW_N Recovery Time Count. This bit field is used
for adjusting the recovery time of IDE0_DIOR_N and IDE0_DIOW_N. See Chapter 11 for details on
programming this timing register.
Bit [15]
: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [14]
: Watchdog Int Ena ( R/W ) – IDE0 Watchdog Interrupt Enable. This bit is set to enable Interrupt when
Watchdog timer expired.
Bit [13]
: Watchdog Ena (R/W) – IDE0 Watchdog Timer Enable. This bit is set to enable the watchdog timer for
IDE0. This bit is cleared to disable the watchdog timer.
Bit [12]
: Watchdog Timeout (R/W1C) – IDE0 Watchdog Timer Timeout. This bit set indicates that the watchdog
timer for IDE0 timed out. When enabled, and IORDY monitoring bit is also enabled, during IDE0 PIO opeartion,
the watchdog counter starts counting when IORDY signal is deasserted. If after 256 PCI clocks cycles, the
IORDY signal is still deasserted, the Watchdog Timer is expires, and this bit is set and the SiI 0680A continue its
operation and stop monitoring IORDY signal. Software writes one to clear this bit. Once this bit is cleared, the SiI
0680A starts monitoring IORDY on channel 0 again.
Bit [11]
: Interrupt Status (R) – IDE0 Interrupt Status. This bit set indicates that an interrupt is pending on IDE0.
This bit provides real-time status of the IDE0 interrupt pin.
Bit [10]
: Virtual DMA Int (R) – IDE0 Virtual DMA Completion Interrupt. This bit set indicates that the Virtual DMA
data transfer has completed. This bit is cleared when bit[0] PBM enable in PCI Bus Master – IDE0 is cleared .
Bit [09]
: IORDY Monitoring (R/W) – IDE0 IORDY Monitoring. When this bit is set, IORDY line is monitored for
Task File accesses on channel 0.
Bit [08:04]
: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [03]
: Channel Tri-State (R/W) – IDE0 Channel Tri-State. This bit is set to tri-state the IDE Channel #0 bus.
This bit is cleared for normal operations.
Bit [02]
: Channel Rst (R/W) – IDE0 Channel Reset. When this bit is set, IDE Channel #0 RST signal is
asserted.
Bit [01]
: Buffered Cmd (R) – IDE0 Buffered Command Active. This bit set indicates that a Buffered Command is
currently active. This bit is set when the first command byte is written to the command buffer. This bit is cleared
when all of the task file bytes, including the command byte, have been written to the device.
Bit [00]
: Cable 80 (R) – IDE0 Cable 80 Detection. This bit provides real-time status of the inverted version of
the IDE0_CBLID_N pin. When set, it indicates that 80 pin cable is detected.
相關PDF資料 |
PDF描述 |
|---|---|
| SII0680 | SteelVine⑩ Host Controller |
| SII1000 | PanelLink Receivers |
| SII1151 | TELECOMMANDER USB(PC&Mac OS X) FOR DESKTOP ROVER |
| SiI1151CLU | CASE,MEDIUM-DUTY ABS,2807, FOAM FILLED,w/HANDLE,BLACK |
| SII1160 | CASE,HEAVY-DUTY POLY,201407, FOAM FILLED,w/HANDLE,BLACK |
相關代理商/技術參數 |
參數描述 |
|---|---|
| SII1000 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PanelLink Receivers |
| SII100N06 | 制造商:SIRECTIFIER 制造商全稱:Sirectifier Semiconductors 功能描述:NPT IGBT Modules |
| SII100N12 | 制造商:SIRECTIFIER 制造商全稱:Sirectifier Semiconductors 功能描述:NPT IGBT Modules |
| SII100S12 | 制造商:SIRECTIFIER 制造商全稱:Sirectifier Semiconductors 功能描述:絕緣柵雙極型晶體管（IGBT）Isolated Gate Bipolar Transistor (IGBTs)，SPT技術的IGBT模塊SPT IGBT Modules (Soft Punch Through Technology)。 |
| SII1151 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PanelLink Receiver |
發(fā)布緊急采購，3分鐘左右您將得到回復。