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參數(shù)資料
| 型號(hào)： | SiI0680ACLU144 |
| 廠(chǎng)商： | Silicon Image, Inc. |
| 英文描述： | PCI to IDE/ATA |
| 中文描述： | PCI到IDE / ATA的 |
| 文件頁(yè)數(shù)： | 87/124頁(yè) |
| 文件大小： | 820K |
| 代理商： | SII0680ACLU144 |
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Silicon Image, Inc.
SiI0680A PCI to IDE/ATA
Data Sheet
2006 Silicon Image, Inc.
SiI-DS-0069-C
87
9.7.29
Address Offset: 90
H
Access Type: Read/Write
Reset Value: 0x0000_0000
IDE0 Task File Register 0 – Command Buffering
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
IDE0 Task File Starting Sector
Number
IDE0 Task File Sector Count
IDE0 Task File Features (W)
IDE0 Task File Error (R)
IDE0 Task File Data
This register defines one of the IDE Channel #0 Task File registers used for Command Buffered accesses in the SiI 0680A.
Access to the individual bytes of this register is determined by the PCI bus Byte Enables at the time of the read or write
operation. The register bits are defined below.
Bit [31:00]
: IDE0 Task File Data (R/W). This bit field defines the IDE0 Task File Data register. This register can
be accessed as an 8-bit, 16-bit, or 32-bit word, depending upon the PCI bus Byte Enables. The data written to
this register must be zero-aligned. To access 8-bit Task File Data, the PCI bus Byte Enable for byte 0 must be
active. To access 16-bit Task File Data, the Byte Enables for byte 1 and byte 0 must be active. To access 32-bit
Task File Data, the Byte Enables for all four bytes must be active.
Bit [31:24]
: IDE0 Task File Starting Sector Number (R/W). This bit field defines the IDE0 Task File Starting
Sector Number register. Access to this bit field is permitted only if the PCI bus Byte Enable for byte 3 is active.
Bit [23:16]
: IDE0 Task File Sector Count (R/W). This bit field defines the IDE0 Task File Sector Count register.
Access to this bit field is permitted only if the PCI bus Byte Enable for byte 2 is active.
Bit [15:08]
: IDE0 Task File Features (W). This write-only bit field defines the IDE0 Task File Features register.
Access to this bit field is permitted only if the PCI bus Byte Enable for byte 1 is active.
Bit [15:08]
: IDE0 Task File Error (R). This read-only bit field defines the IDE0 Task File Error register. Access
to this bit field is permitted only if the PCI bus Byte Enable for byte 1 is active.
9.7.30
Address Offset: 94
H
Access Type: Read/Write
Reset Value: 0x0000_0000
IDE0 Task File Register 1 – Command Buffering
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
IDE0 Task File Command + Status
IDE0 Task File Device+Head
IDE0 Task File Cylinder High
IDE0 Task File Cylinder Low
This register defines one of the IDE Channel #0 Task File registers used for Command Buffered accesses in the SiI 0680A.
The register bits are defined below.
Bit [31:24]
: IDE0 Task File Command (W). This write-only bit field defines the IDE0 Task File Command
register.
Bit [31:24]
: IDE0 Task File Status (R). This read-only bit field defines the IDE0 Task File Status register.
Bit [23:16]
: IDE0 Task File Device+Head (R/W). This bit field defines the IDE0 Task File Device and Head
register.
Bit [15:08]
: IDE0 Task File Cylinder High (R/W). This bit field defines the IDE0 Task File Cylinder High register.
Bit [07:00]
: IDE0 Task File Cylinder Low (R/W). This bit field defines the IDE0 Task File Cylinder Low register.
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