參數(shù)資料
型號： SiI0680ACLU144
廠商： Silicon Image, Inc.
英文描述： PCI to IDE/ATA
中文描述： PCI到IDE / ATA的
文件頁數(shù)： 106/124頁
文件大?。?/td> 820K
代理商： SII0680ACLU144
SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0069-C
106
21
IDE0_DA2
53
IDE1_CBLID_N
85
PCI_SERR_N
22
IDE0_DIOR_N
54
IDE1_DMACK_N
86
PCI_PAR
23
IDE0_DIOW_N
55
IDE1_INTRQ
87
PCI_CBE1
24
IDE0_DMACK_N
56
IDE1_IORDY
88
PCI_AD15
25
IDE0_CBLID_N
57
IDE1_DMARQ
89
PCI_AD14
26
IDE0_INTRQ
58
IDE1_RST_N
90
PCI_AD13
27
IDE0_IORDY
59
JP
91
PCI_AD12
28
IDE0_DMARQ
60
PCI_AD31
92
PCI_AD11
29
IDE0_RST_N
61
PCI_AD30
93
PCI_AD10
30
IDE1_DD00
62
PCI_AD29
94
PCI_AD09
31
IDE1_DD01
63
PCI_AD28
95
PCI_AD08
32
IDE1_DD02
64
PCI_AD27
96
PCI_CBE0
97
PCI_AD07
102
PCI_AD02
107
BA5_EN
98
PCI_AD06
103
PCI_AD01
108
PCI_CLK
99
PCI_AD05
104
PCI_AD00
109
SCAN_EN
100
PCI_AD04
105
PCI_REQ_N
110
MEM_CS_N
101
PCI_AD03
106
PCI_GNT_N
Table 10-2, SiI 0680A NAND Tree Order (continued)
10.3 Full Chip Internal Scan
The SiI 0680A generates SCAN_MODE internal signal by asserting logic “1” on the following input pins TEST_MODE,
BA5_EN, and PCI_GNT_N.
The SCAN_MODE signal selects the source for the scan clocks and sets internal latches open during scan. The internal
clocks for scan are provided as shown in Fig. 10-1, by the following pins:
External Input Pins:
Internal Scan Clock:
PCI_CLK
P_CLK
IDE0_CBLID
I0_CLK
IDE1_CBLID
I1_CLK
Additionally, SCAN_EN selects between normal inputs and scan inputs at all the scan flip-flops is provided by the input pin
SCAN_EN.
There are six scan chains with input pins and output pins as follows:
SCAN CHAIN
SCAN INPUT PIN
1
IDE0_DMARQ
2
IDE0_INTRQ
3
IDE0_IORDY
4
IDE1_DMARQ
5
IDE1_INTRQ
6
IDE1_IORDY
SCAN OUTPUT PIN
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
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