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參數(shù)資料
| 型號： | SiI0680ACLU144 |
| 廠商： | Silicon Image, Inc. |
| 英文描述： | PCI to IDE/ATA |
| 中文描述： | PCI到IDE / ATA的 |
| 文件頁數(shù)： | 110/124頁 |
| 文件大?。?/td> | 820K |
| 代理商： | SII0680ACLU144 |
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SiI0680A PCI to IDE/ATA
Data Sheet
program into this register for each PIO mode. If there is more than one device attached to the channel,
select the PIO mode of the slowest device. If PIO mode 3 or 4 is selected, bit 9 of the IDEx Task File
Timing + Configuration + Status register must also be set to enable the controller to monitor the state of the
IORDY signal.
Set the PIO data transfer timing. The PIO data transfer timing is set by programming bits [15:0] for device 0,
or bits [31:16] for device 1, of the IDEx PIO Timing register. See section 13.2.2 for recommended values to
program into this register for each PIO mode. The default value of this register sets the timing slow enough
to work with any ATA/ATAPI device, so this step is optional if the ATA/ATAPI device will not be used in PIO
mode.
Set the multiword DMA data transfer timing. This step is necessary only if the ATA/ATAPI device will be
operated in a multiword DMA mode. The multiword DMA timing is set by programming bits [15:0] for device
0, or bits [31:16] for device 1, of the IDEx DMA Timing register. See section 13.2.3 for recommended values
to program into this register for each multiword DMA mode.
Set the Ultra DMA data transfer timing. This step is necessary only if the ATA/ATAPI device will be operated
in an Ultra DMA mode. The Ultra DMA timing is set by programming bits [15:0] for device 0, or bits [31:16]
for device 1, of the IDEx UDMA Timing register. See sections 13.2.4 and 13.2.5 for recommended values to
program into this register for each Ultra DMA mode.
In order to use the controller’s DMA capability to perform the data transfer for an ATA/ATAPI command, the
controller needs to be configured for the transfer mode to use when transferring data to or from the ATA bus.
The data transfer mode is set by programming bits [1:0] for device 0, or bits [5:4] for device 1, of the IDEx
Data Transfer Mode register. The transfer mode select values are listed below:
00
B
= PIO Mode without IORDY monitoring
01
B
= PIO Mode with IORDY monitoring
10
B
= Multiword DMA
11
B
= Ultra DMA
NOTE:
When using PIO to perform a data transfer, this register only instructs the controller as to whether or not it should
monitor the IORDY signal when the task file data register is accessed. Any value other than 00
H
will cause the
controller to monitor the IORDY signal.
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0069-C
110
11.4 Issue ATA Command
The following describes the sequence to issue a read/write type command to an ATA device.
Select the IDE device. The IDE device is selected by programming bits [23:16] in the IDEx Task File
Register 1 register.
Set the number of sectors to be transferred by programming bits [23:16] of the IDEx Task File Register 0
register.
Set the location of data to be transferred. The location is defined by programming the following.
Bits [31:24] in the IDEx Task File Register 0 register define the Starting Sector.
Bits [23:16] in the IDEx Task File Register 1 register define the Device and Head value.
Bits [15:08] in the IDEx Task File Register 1 register define the Cylinder High value.
Bits [07:00] in the IDEx Task File Register 1 register define the Cylinder Low value.
Issue the Read/Write PIO/DMA command by programming bits [31:24] in the IDEx Task File Register 1
register with the command desired.
11.5 IDE PIO Mode Read/Write Operation
Once the SiI 0680A is initialized via the initialization sequence described in Section 11.1, the ATA device has been initialized
for PIO mode data transfer per the guidelines in section 11.2, and the controller channel has been initialized for PIO mode data
transfer per the instructions in section 11.3, PIO read/write operations may be performed by following the programming
sequence described below.
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