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參數(shù)資料
| 型號(hào)： | SiI0680ACLU144 |
| 廠商： | Silicon Image, Inc. |
| 英文描述： | PCI to IDE/ATA |
| 中文描述： | PCI到IDE / ATA的 |
| 文件頁數(shù)： | 111/124頁 |
| 文件大?。?/td> | 820K |
| 代理商： | SII0680ACLU144 |
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Silicon Image, Inc.
Issue a PIO Read/Write command to device following the steps in section 11.4.
Read Operation
Wait until an IDE channel interrupt (bit 11 in the IDEx Task File Timing + Configuration + Status register is
set).
Read the device status at bits [31:24] in the IDEx Task File Register 1 register to clear the device interrupt
and determine if there was error.
If no error, continue to read IDE data via the IDEx Task File Register 0 register, until the expected number of
sectors of data per interrupt are read.
Repeat the above three steps until all data for the read command has been transferred or an error has been
detected.
Write Operation
Wait until bit 27(DRQ) in the IDEx Task File Register 1 register is set.
Continue to write IDE data via the IDEx Task File Register 0 register until the expected number of sectors of
data per interrupt are written.
Wait until an IDE channel interrupt (bit 11 in the IDEx Task File Timing + Configuration + Status register is
set).
Read the device status at bits [31:24] in the IDEx Task File Register 1 register to clear the device interrupt
and determine if there was error.
If no error, repeat the previous four steps until all data for the write command has been transferred or an error has been
detected.
SiI0680A PCI to IDE/ATA
Data Sheet
2006 Silicon Image, Inc.
SiI-DS-0069-C
111
11.6 Watchdog Timer Operation
The purpose of the watchdog timer is to prevent the host system from hanging because a device operating in PIO mode
stopped responding to task file accesses. In PIO modes 0, 1, and 2, device access is completely controlled by the values
programmed into the Task File Timing and PIO Timing registers. In these modes it is not possible for a non-responsive device
to hang-up the host system. However, in PIO modes 3 and 4, device task file accesses are not regulated by the timing
registers alone, but can also be controlled by the device through the use of the IORDY signal. If, during a task file access by
the host, the device negates IORDY and then stops responding, the host will hang waiting for the access to complete. It is this
type of hang, that the watchdog timer is designed to protect against.
The watchdog timer monitors the length of time the IORDY signal is negated. If the watchdog timer detects that the the IORDY
signal has remained negated longer than the watchdog timeout period (approximately 7.75us), the watchdog timer will force
the task file access cycle to complete, and set the watchdog timeout bit in the IDEx Task File Timing + Configuration + Status
register. The data associated with a timed out access should be considered invalid. Additionally, the watchdog timer can be
configured to generate an interrupt when a timeout is detected by setting bit 14 of the IDEx Task File Timing + Configuration +
Status register.
The watchdog timer feature is disabled by default.
In addition to the controller channel initialization specified in section 11.3, add the following two steps to enable the watchdog
timer:
Enable the watchdog timer by setting bit 13 of the IDEx Task File Timing + Config + Status register.
If an interrupt is desired whenever the watchdog times out, enable the watchdog interrupt by setting bit 14 of
the IDEx Task File Timing + Config + Status register.
The following programming sequences are needed for each PIO Mode 3 or 4 Read/Write Operation with the watchdog timer
enabled:
Issue a Read/Write PIO Command to the ATA drive following the steps in section 11.4.
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