參數(shù)資料
型號： SiI0680ACLU144
廠商： Silicon Image, Inc.
英文描述： PCI to IDE/ATA
中文描述： PCI到IDE / ATA的
文件頁數(shù)： 84/124頁
文件大?。?/td> 820K
代理商： SII0680ACLU144
SiI0680A PCI to IDE/ATA
Data Sheet
9.7.23
FIFO Pointers1– IDE1
Address Offset: 78
H
Access Type: Read Only
Reset Value: 0x0000_0000
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0069-C
84
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
FIFO Byte 1 Wr Pointer – IDE1
FIFO Byte 1 Rd Pointer – IDE1
FIFO Byte 0 Wr Pointer – IDE1
FIFO Byte 0 Rd Pointer – IDE1
This register provides visibility into the data FIFO for IDE Channel #1 in the SiI 0680A. The data FIFO is organized as a
four byte-wide x 64 deep memory array. There are separate write and read pointer for each of the byte slices. This
register is used for hardware debugging purposes only. The register bits are defined below.
Bit [31:24]
: FIFO Byte 1 Wr Pointer – IDE1 (R) FIFO Byte 1 Write Pointer. This bit field provides the status on
the write pointer for Byte 1.
Bit [23:16]
: FIFO Byte 1 Rd Pointer – IDE1 (R) FIFO Byte 1 Read Pointer. This bit field provides the status on
the read pointer for Byte 1.
Bit [15:08]
: FIFO Byte 0 Wr Pointer – IDE1 (R) FIFO Byte 0 Write Pointer. This bit field provides the status on
the write pointer for Byte 0.
Bit [07:00]
: FIFO Byte 0 Rd Pointer – IDE1 (R) FIFO Byte 0 Read Pointer. This bit field provides the status on
the read pointer for Byte 0.
9.7.24
FIFO Pointers2– IDE1
Address Offset: 7C
H
Access Type: Read Only
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
FIFO Byte 3 Wr Pointer – IDE1
FIFO Byte 3 Rd Pointer – IDE1
FIFO Byte 2 Wr Pointer – IDE1
FIFO Byte 2 Rd Pointer – IDE1
This register provides visibility into the data FIFO for IDE Channel #1 in the SiI 0680A. The data FIFO is organized as a
four byte-wide x 64 deep memory array. There are separate write and read pointer for each of the byte slices. This
register is used for hardware debugging purposes only. The register bits are defined below.
Bit [31:24]
: FIFO Byte 3 Wr Pointer – IDE1 (R) FIFO Byte 3 Write Pointer. This bit field provides the status on
the write pointer for Byte 3.
Bit [23:16]
: FIFO Byte 3 Rd Pointer – IDE1 (R) FIFO Byte 3 Read Pointer. This bit field provides the status on
the read pointer for Byte 3.
Bit [15:08]
: FIFO Byte 2 Wr Pointer – IDE1 (R) FIFO Byte 2 Write Pointer. This bit field provides the status on
the write pointer for Byte 2.
Bit [07:00]
: FIFO Byte 2 Rd Pointer – IDE1 (R) FIFO Byte 2 Read Pointer. This bit field provides the status on
the read pointer for Byte 2.
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