參數(shù)資料
型號(hào)： SiI0680ACLU144
廠商： Silicon Image, Inc.
英文描述： PCI to IDE/ATA
中文描述： PCI到IDE / ATA的
文件頁數(shù)： 79/124頁
文件大?。?/td> 820K
代理商： SII0680ACLU144
Silicon Image, Inc.
9.7.13
System Configuration Status – Command
Address Offset: 48
H
Access Type: Read/Write
Reset Value: 0x0000_0000
SiI0680A PCI to IDE/ATA
Data Sheet
2006 Silicon Image, Inc.
SiI-DS-0069-C
79
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
B
Reserved
I
I
I
Reserved
I
I
F
F
R
A
P
This register defines the system configuration status and command register for the SiI 0680A. The register bits are
defined below.
Bit [31:24]
: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [23]
: IDE1 Int Block (R/W) – IDE1 Interrupt Block. This bit is set to block interrupts from the IDE Channel #1
to the PCI bus.
Bit [22]
: IDE0 Int Block (R/W) – IDE0 Interrupt Block. This bit is set to block interrupts from the IDE Channel #0
to the PCI bus.
Bit [21:20]
: IDE Clk Select (R/W) – IDE Clock Frequency Select. This bit field is used set the IDE clock
frequency for both IDE modules: 00
B
= 100 MHz; 01
B
= 133 MHz; 10
B
= PCI Clock x 2; and, 11
B
= IDE Clock
Disabled.
Bit [19:17]
: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [16]
: BA5_EN (R) – Base Address 5 Enable. This bit reflects input pin BA5_EN.
Bit [15:08]
: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [07]
: IDE0 Module Rst (R/W) – IDE0 Module Reset. This bit is set to reset the interface logic for the IDE
Channel #0.
Bit [06]
: IDE1 Module Rst (R/W) – IDE1 Module Reset. This bit is set to reset the interface logic for the IDE
Channel #1.
Bit [05]
: FF0 Module Rst (R/W) – FF0 Module Reset. This bit is set to reset the logic in the FIFO for IDE
Channel #0.
Bit [04]
: FF1 Module Rst (R/W) – FF1 Module Reset. This bit is set to reset the logic in the FIFO for IDE
Channel #1.
Bit [03:02]
: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [01]
: ARB Module Rst (R/W) – ARB Module Reset. This bit is set to reset the internal logic for the PCI-IDE
arbiter.
Bit [00]
: PBM Module Rst (R/W) – PBM Module Reset. This bit is set to reset the internal logic for the PCI bus
master state machine.
9.7.14
System Software Data Register
Address Offset: 4C
H
Access Type: Read/Write
Reset Value: Undefined
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
System Software Data
This register is used by the software for non-resettable data storage. The contents are unknown on power-up and are never
cleared by any type of reset.
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