參數(shù)資料
型號： SiI0680ACLU144
廠商： Silicon Image, Inc.
英文描述： PCI to IDE/ATA
中文描述： PCI到IDE / ATA的
文件頁數(shù)： 59/124頁
文件大小： 820K
代理商： SII0680ACLU144
Silicon Image, Inc.
9.1.29
EEPROM Memory Address – Command + Status
Address Offset: 98
H
Access Type: Read/Write
Reset Value: 0x0000_0000
SiI0680A PCI to IDE/ATA
Data Sheet
2006 Silicon Image, Inc.
SiI-DS-0069-C
59
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
M
Reserved
M
M
R
M
Reserved
Mem Address
This register defines the address and command/status register for EEPROM memory interface in the SiI 0680A. The register
bits are also mapped to Base Address 5, Offset 58
H
. See Section 9.7.17 for bit definitions.
9.1.30
Address Offset: 9C
H
Access Type: Read/Write
Reset Value: 0x0000_0000
EEPROM Memory Data
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
Memory Data
This register defines the data register for EEPROM memory interface in the SiI 0680A. The register bits are also mapped to
Base Address 5, Offset 5C
H
. See Section 9.7.18 for bit definitions.
9.1.31
Address Offset: A0
H
Access Type: Read/Write
Reset Value: 0x6515_0100
IDE0 Task File Timing + Configuration + Status
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Addr Setup
Count
Active Count
Recovery Count
R
W
W
W
I
V
I
R
Reserved
C
C
B
C
This register defines the task file timing register for IDE Channel #0 in the SiI 0680A. The register bits are also mapped to
Base Address 5, Offset A0
H
. See Section 9.7.33 for bit definitions.
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