- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄365565 > SiI0680ACL144 (Silicon Image, Inc.) PCI to IDE/ATA PDF資料下載
參數(shù)資料
| 型號： | SiI0680ACL144 |
| 廠商： | Silicon Image, Inc. |
| 英文描述： | PCI to IDE/ATA |
| 中文描述： | PCI到IDE / ATA的 |
| 文件頁數(shù)： | 94/124頁 |
| 文件大?。?/td> | 820K |
| 代理商： | SII0680ACL144 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁當(dāng)前第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁
SiI0680A PCI to IDE/ATA
Data Sheet
9.7.38
Data Transfer Mode – IDE0
Address Offset: B4
H
Access Type: Read/Write
Reset Value: 0x0000_0022
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0069-C
94
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
R
I
T
R
I
T
This register defines the transfer mode register for IDE Channel #0 in the SiI 0680A. The register bits are defined below.
Bit [31:08]
: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [07:06]
: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [05:04]
: Device 1 Transfer Mode (R/W) – IDE0 Device 1 Data Transfer Mode. This bit field is used to set the
data transfer mode on IDE side during PCI DMA transfer: 00
B
= PIO transfer with IORDY not monitored; 01
B
=
PIO transfer with IORDY monitored; 10
B
= normal DMA; and, 11
B
= Ultra DMA.
When this bit field is set to value other than 00
B
, SiI 0680A will monitor IORDY for normal PIO transfer.
Bit [03:02]
: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [01:00]
: Device 0 Transfer Mode (R/W) – IDE0 Device 0 Data Transfer Mode. This bit field is used to set the
data transfer mode on IDE side during PCI DMA transfer: 00
B
= PIO transfer with IORDY not monitored; 01
B
=
PIO transfer with IORDY monitored; 10
B
= normal DMA; and, 11
B
= Ultra DMA.
When this bit field is set to value other than 00
B
, SiI 0680A will monitor IORDY for normal PIO transfer.
9.7.39
IDE1 Task File Register 0
Address Offset: C0
H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
IDE1 Task File Starting Sector
Number
IDE1 Task File Sector Count
IDE1 Task File Features (W)
IDE1 Task File Error (R)
IDE1 Task File Data
This register defines one of the IDE Channel #1 Task File registers in the SiI 0680A. Access to the individual bytes of this
register is determined by the PCI bus Byte Enables at the time of the read or write operation. The register bits are defined
below.
Bit [31:00]
: IDE1 Task File Data (R/W). This bit field defines the IDE1 Task File Data register. This register can
be accessed as an 8-bit, 16-bit, or 32-bit word, depending upon the PCI bus Byte Enables. The data written to
this register must be zero-aligned. To access 8-bit Task File Data, the PCI bus Byte Enable for byte 0 must be
active. To access 16-bit Task File Data, the Byte Enables for byte 1 and byte 0 must be active. To access 32-bit
Task File Data, the Byte Enables for all four bytes must be active.
Bit [31:24]
: IDE1 Task File Starting Sector Number (R/W). This bit field defines the IDE1 Task File Starting
Sector Number register. Access to this bit field is permitted if the PCI bus Byte Enable is active for this byte only.
Bit [23:16]
: IDE1 Task File Sector Count (R/W). This bit field defines the IDE1 Task File Sector Count register.
Access to this bit field is permitted if the PCI bus Byte Enable is active for this byte only.
Bit [15:08]
: IDE1 Task File Features (W). This write-only bit field defines the IDE1 Task File Features register.
Access to this bit field is permitted if the PCI bus Byte Enable is active for this byte only.
Bit [15:08]
: IDE1 Task File Error (R). This read-only bit field defines the IDE1 Task File Error register. Access
to this bit field is permitted if the PCI bus Byte Enable is active for this byte only.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SiI0680ACLU144 | PCI to IDE/ATA |
| SII0680 | SteelVine⑩ Host Controller |
| SII1000 | PanelLink Receivers |
| SII1151 | TELECOMMANDER USB(PC&Mac OS X) FOR DESKTOP ROVER |
| SiI1151CLU | CASE,MEDIUM-DUTY ABS,2807, FOAM FILLED,w/HANDLE,BLACK |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SII0680ACLU144 | 制造商:Silicon Image Inc 功能描述:STEELVINE HOST CONTROLLER |
| SII1000 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PanelLink Receivers |
| SII100N06 | 制造商:SIRECTIFIER 制造商全稱:Sirectifier Semiconductors 功能描述:NPT IGBT Modules |
| SII100N12 | 制造商:SIRECTIFIER 制造商全稱:Sirectifier Semiconductors 功能描述:NPT IGBT Modules |
| SII100S12 | 制造商:SIRECTIFIER 制造商全稱:Sirectifier Semiconductors 功能描述:絕緣柵雙極型晶體管（IGBT）Isolated Gate Bipolar Transistor (IGBTs)，SPT技術(shù)的IGBT模塊SPT IGBT Modules (Soft Punch Through Technology)。 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。