參數(shù)資料
型號(hào)： SiI0680ACL144
廠商： Silicon Image, Inc.
英文描述： PCI to IDE/ATA
中文描述： PCI到IDE / ATA的
文件頁(yè)數(shù)： 71/124頁(yè)
文件大?。?/td> 820K
代理商： SII0680ACL144
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Silicon Image, Inc.
Address
Offset
SiI0680A PCI to IDE/ATA
Data Sheet
2006 Silicon Image, Inc.
SiI-DS-0069-C
71
Register Name
31
16
15
00
Access
Type
CC
H
IDE1 Read Ahead Data
R/W
D0
H
IDE1 TF Starting
Sector Number2
IDE1 TF Sector
Count2
IDE1 TF
Features2 IDE1
TF Error2
Reserved
R/W
D4
H
IDE1 TF
Cmd+Sts2
IDE1 TF
Device+Head2
IDE1 TF Cylinder
High2
IDE1 TF Cylinder
Low2
R/W
D8
H
Reserved
-
DC
H
IDE1 Virtual DMA/PIO Read Ahead Byte Count
R/W
E0
H
IDE1 TF Timing
IDE1 Config
+ Status
IDE1 Cmd
+ Status
R/W
E4
H
IDE1 Device 1 PIO Timing
IDE1 Device 0 PIO Timing
R/W
E8
H
IDE1 Device 1 DMA Timing
IDE1 Device 0 DMA Timing
R/W
EC
H
IDE1 Device 1 UDMA Timing
IDE1 Device 0 UDMA Timing
R/W
F0
H
IDE1 Test Register
R/W
F4
H
Reserved
IDE1 Data
Transfer Mode
R/W
F8
H
Reserved
-
FC
H
Reserved
-
Table 9-7: SiI 0680A Internal Register Space – Base Address 5
9.7.1
Address Offset: 00
H
Access Type: Read/Write
Reset Value: 0x0000_XX00
PCI Bus Master – IDE0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
P
P
P
R
I
P
P
I
I
Software
Reserved
P
R
P
This register defines the PCI bus master register for IDE Channel #0 in the SiI 0680A. The register bits are defined below.
Bit [31:24]
: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [23]
: PBM Simplex (R) – PCI Bus Master Simplex Only. This read-only bit field is hardwired to zero to
indicate that both IDE channels can operate as PCI bus master at any time.
Bit [22]
: PBM DMA Cap 1 (R/W) – PCI Bus Master DMA Capable – Device 1. This bit field has no effect. The
device is always capable of DMA as a PCI bus master.
Bit [21]
: PBM DMA Cap 0 (R/W) – PCI Bus Master DMA Capable – Device 0. This bit field has no effect. The
device is always capable of DMA as a PCI bus master.
Bit [20:19]
: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [18]
: IDE0 DMA Comp (R/W1C) – IDE0 DMA Completion Interrupt. During write DMA operation, This bit set
indicates that the IDE0 interrupt has been asserted and all data has been written to system memory. During
Read
DMA,
This
bit
set
indicates
that
the
IDE0
interrupt
has
been
asserted.
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