參數資料
型號： SiI0680ACL144
廠商： Silicon Image, Inc.
英文描述： PCI to IDE/ATA
中文描述： PCI到IDE / ATA的
文件頁數： 100/124頁
文件大?。?/td> 820K
代理商： SII0680ACL144
SiI0680A PCI to IDE/ATA
Data Sheet
9.7.49
IDE1 DMA Timing
Address Offset: E8
H
Access Type: Read/Write
Reset Value: 0x4392_4392
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0069-C
100
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Device 1 Addr
Setup Count
Device 1 Active Count
Device 1 Recovery
Count
Device 0 Addr
Setup Count
Device 0 Active Count
Device 0 Recovery
Count
This register defines the DMA timing register for IDE Channel #1 in the SiI 0680A. See chapter 11 for details on
programming this timing register. The register bits are defined below.
Bit [31:28]
: Device 1 Addr Setup Count (R/W) – IDE1 Device 1 Address Setup Time Count for DMA Mode. This
bit field is used for programming the address setup time relative to IDE1_DIOR_N and IDE1_DIOW_N in DMA
mode.
Bit [27:22]
: Device 1 Active Count (R/W) – IDE1 Device 1 DIOR_N and DIOW_N Active Time Count for DMA
Mode. This bit field is used for programming the active time of IDE1_DIOR_N and IDE1_DIOW_N in DMA mode.
Bit [21:16]
: Device 1 Recovery Count (R/W) – IDE1 Device 1 DIOR_N and DIOW_N Recovery Time Count for
DMA Mode. This bit field is used for programming the recovery time of IDE1_DIOR_N and IDE1_DIOW_N in
DMA mode.
Bit [15:12]
: Device 0 Addr Setup Count (R/W) – IDE1 Device 0 Address Setup Time Count for DMA Mode. This
bit field is used for programming the address setup time relative to IDE1_DIOR_N and IDE1_DIOW_N in DMA
mode.
Bit [11:06]
: Device 0 Active Count (R/W) – IDE1 Device 0 DIOR_N and DIOW_N Active Time Count for DMA
Mode. This bit field is used for programming the active time of IDE1_DIOR_N and IDE1_DIOW_N in DMA mode.
Bit [05:00]
: Device 0 Recovery Count (R/W) – IDE1 Device 0 DIOR_N and DIOW_N Recovery Time Count for
DMA Mode. This bit field is used for programming the recovery time of IDE1_DIOR_N and IDE1_DIOW_N in
DMA mode.
9.7.50
IDE1 UDMA Timing
Address Offset: EC
H
Access Type: Read/Write
Reset Value: 0x4009_4009
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
D
D
D
D
D
H
R
Device 1 Cycle Time
Count
D
D
D
D
D
H
R
Device 0 Cycle Time
Count
This register defines the UDMA timing register for IDE Channel #1 in the SiI 0680A. See chapter 11 for details on
programming this timing register. The register bits are defined below.
Bit [31:30]
: Device 1 Data Input Delay (R/W) – IDE1 Device 1 Data Input Delay for UDMA Mode. This bit field is
used for programming the data input delay in increments of 2 nsec in UDMA mode.
Bit [29:28]
: Device 1 DSTROBE Delay (R/W) – IDE1 Device 1 DSTROBE Delay for UDMA Mode. This bit field
is used for programming the DSTROBE output delay in increments of 2 nsec in UDMA mode.
Bit [27:25]
: Device 1 HSTROBE Delay (R/W) – IDE1 Device 1 HSTROBE Delay for UDMA Mode. This bit field
is used for programming the HSTROBE output delay in increments of 2 nsec in UDMA mode.
Bit [24:23]
: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [22]
: Reserved (R/W) – This bit field is reserved.
Bit [21:16]
: Device 1 Cycle Time Count (R/W) – IDE1 Device 1 UDMA Cycle Time Count. This bit field is used
for programming the UDMA Active and Recovery Time.
Bit [15:14]
: Device 0 Data Input Delay (R/W) – IDE1 Device 0 Data Input Delay for UDMA Mode. This bit field is
used for programming the data input delay in increments of 2 nsec in UDMA mode.
Bit [13:12]
: Device 0 DSTROBE Delay (R/W) – IDE1 Device 0 DSTROBE Delay for UDMA Mode. This bit field
is used for programming the DSTROBE output delay in increments of 2 nsec in UDMA mode.
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