參數(shù)資料
型號： SiI0680ACL144
廠商： Silicon Image, Inc.
英文描述： PCI to IDE/ATA
中文描述： PCI到IDE / ATA的
文件頁數(shù)： 109/124頁
文件大?。?/td> 820K
代理商： SII0680ACL144
Silicon Image, Inc.
SiI0680A PCI to IDE/ATA
Data Sheet
2006 Silicon Image, Inc.
SiI-DS-0069-C
109
enabled, command completion can be detected by polling bits [31:24] of the IDEx Task
File Register 1 register until the BUSY bit is no longer asserted.
If device supports read/write multiple commands, issue the Set Multiple Mode command by:
Programming bits [23:16] in the IDEx Task File 0 register with the number of sectors per
block to use on the following Read/Write Multiple commands.
Programming bits [31:24] in the IDEx Task File Register 1 register with the value = C6
H
.
Wait for the command to complete (see above).
For both ATA and ATAPI devices:
Set device transfer mode by:
Programming bits [15:08] in the IDEx Task File 0 register with the value 03
H
to “Set the
transfer mode based on value in Sector Count Register”.
Programming bits [23:16] in the IDEx Task File 0 register to the desired transfer mode.
The settings are defined below:
08
H
= PIO Mode 0
09
H
= PIO Mode 1
0A
H
= PIO Mode 2
0B
H
= PIO Mode 3
0C
H
= PIO Mode 4
20
H
= Multiword DMA Mode 0
21
H
= Multiword DMA Mode 1
22
H
= Multiword DMA Mode 2
40
H
= Ultra DMA Mode 0
41
H
= Ultra DMA Mode 1
42
H
= Ultra DMA Mode 2
43
H
= Ultra DMA Mode 3
44
H
= Ultra DMA Mode 4
45
H
= Ultra DMA Mode 5
46
H
= Ultra DMA Mode 6
Programming bits [31:24] in the IDEx Task File Register 1 register with the value = EF
H
.
Wait for the command to complete (see above).
NOTE: An 80-pin cable is required to ensure signal quality can be maintained for transfer modes
higher than Ultra DMA mode 2. When bit 0 of the IDEx Task File Timing + Configuration + Status
register is set, an 80-pin cable may be present (see the ATA/ATAPI specification for details on how
this bit should be interpreted).
11.3 Initialization of Controller Channel Timing Registers
There are four types of timing registers associated with a channel.
The IDEx Task File Timing + Configuration + Status register controls the timing of ATA/ATAPI device task file register
accesses (except for accesses to the data register). Since this register controls the task file access timing for all devices
attached to the channel, it is important to program this register with values that do not exceed the capabilities of the slowest
device attached to the channel.
The IDEx PIO Timing register controls the access timing of the task file data register when programmed I/O is used to transfer
data to or from the device.
The IDEx DMA Timing register controls the data transfer timing when the device and controller have been setup to use a
multiword DMA transfer mode.
The IDEx UDMA Timing register controls the data transfer timing when the device and controller have been setup to use an
Ultra DMA transfer mode.
Data transfer timing can be set independently for each device. The following steps need to be performed to configure the
controller timing to match the transfer mode selected for the ATA/ATAPI device:
Set the task file register access timing. The task file register timing is set by programming bits [31:16] of the
IDEx Task File Timing + Configuration + Status register. See section 13.2.1 for recommended values to
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