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參數(shù)資料
| 型號(hào)： | SiI0680ACL144 |
| 廠商： | Silicon Image, Inc. |
| 英文描述： | PCI to IDE/ATA |
| 中文描述： | PCI到IDE / ATA的 |
| 文件頁(yè)數(shù)： | 53/124頁(yè) |
| 文件大?。?/td> | 820K |
| 代理商： | SII0680ACL144 |
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Silicon Image, Inc.
9.1.12
Expansion ROM Base Address
Address Offset: 30
H
Access Type: Read/Write
Reset Value: 0x0000_0000
SiI0680A PCI to IDE/ATA
Data Sheet
2006 Silicon Image, Inc.
SiI-DS-0069-C
53
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Expansion ROM Base Address
Not Used
E
This register defines the Expansion ROM base address associated with the PCI bus. The register bits are defined below.
Bit [31:19]
: Expansion ROM Base Address (R/W) – Expansion ROM Base Address. This bit field defines the
upper bits of the Expansion ROM base address.
Bit [18:01]
: Not Used (R). This bit field is hardwired to 00000
H
. The minimum Expansion ROM address range
is 512K bytes.
Bit [00]
: Exp ROM Enable (R/W) – Expansion ROM Enable. This bit is set to enable the Expansion ROM
access.
9.1.13
Address Offset: 34
H
Access Type: Read
Reset Value: 0x0000_0060
Capabilities Pointer
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
Capabilities Pointer
This register defines the link to a list of new capabilities associated with the PCI bus. The register bits are defined below.
Bit [31:08]
: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [07:00]
: Capabilities Pointer (R) – Capabilities Pointer. This bit field defaults to 60
H
to define the address for
the 1
entry in a list of PCI Power Management capabilities.
9.1.14
Address Offset: 3C
H
Access Type: Read/Write
Reset Value: 0x0000_0100
Max Latency – Min Grant – Interrupt Pin – Interrupt Line
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Max Latency
Min Grant
Interrupt Pin
Interrupt Line
This register defines the various control functions associated with the PCI bus. The register bits are defined below.
Bit [31:24]
: Max Latency (R) – Maximum Latency. This bit field is hardwired to 00
H
.
Bit [23:16]
: Min Grant (R) – Minimum Grant. This bit field is hardwired to 00
H
.
Bit [15:08]
: Interrupt Pin (R) – Interrupt Pin Used. This bit field is hardwired to 01
H
to indicate that the SiI 0680A
uses the INTA# interrupt.
Bit [07:00]
: Interrupt Line (R/W) – Interrupt Line. This bit field is used by the system to indicate interrupt line
routing information. The SiI 0680A does not use this information.
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| SiI0680ACLU144 | PCI to IDE/ATA |
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| SII0680ACLU144 | 制造商:Silicon Image Inc 功能描述:STEELVINE HOST CONTROLLER |
| SII1000 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PanelLink Receivers |
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