參數(shù)資料
型號： SiI0680ACL144
廠商： Silicon Image, Inc.
英文描述： PCI to IDE/ATA
中文描述： PCI到IDE / ATA的
文件頁數(shù)： 112/124頁
文件大?。?/td> 820K
代理商： SII0680ACL144
SiI0680A PCI to IDE/ATA
Data Sheet
Read Operation
Wait for an IDE channel interrupt.
If controller interrupts are disabled, poll for the IDE interrupt by reading the IDEx Task File Timing +
Configuration + Status register. If bit 12 is set, a watchdog timeout has occurred. If bit 11 is set,
the ATA device is interrupting.
If the watchdog timeout bit is set,
Write 1 to bit 12 in the IDEx Task File Timing + Configuration + Status register to clear watchdog
timeout status.
The watchdog timeout represents a fatal error as far as the current ATA command is concerned. A
course of action that might be appropriate at this point might be to reset and reinitialize the ATA
channel and then retrying the command that failed.
If the ATA device interrupt bit is set,
Read the device status at bits [31:24] in the IDEx Task File Register 1 register to clear the device
interrupt and determine if there was an error.
Write 1 to bit 18 of the PCI Bus Master – IDEx Register to i clear the latched interrupt status. Note
that clearing the PCI interrupt does not clear bit 18 as this bit needs to be cleared separately.
If the ATA device is not reporting an error, continue to read IDE data via the IDEx Task File
Register 0 register, until the expected number of sectors of data per interrupt are read.
Repeat the read operation steps until all data for the read command has been transferred or an error has
been detected.
Write Operation
Wait until bit 27(DRQ) in the IDEx Task File Register 1 register is set.
Continue to write IDE data via the IDEx Task File Register 0 register until the expected number of sectors of
data per interrupt are written.
Wait for an IDE channel interrupt.
If controller interrupts are disabled, poll for the IDE interrupt by reading the IDEx Task File Timing +
Configuration + Status register. If bit 12 is set, a watchdog timeout has occurred. If bit 11 is set,
the ATA device is interrupting.
If the watchdog timeout bit is set,
Write 1 to bit 12 in the IDEx Task File Timing + Configuration + Status register to clear watchdog
timeout status.
The watchdog timeout represents a fatal error as far as the current ATA command is concerned. A
course of action that might be appropriate at this point might be to reset and reinitialize the ATA
channel and then retrying the command that failed.
If the ATA device interrupt bit is set,
Read the device status at bits [31:24] in the IDEx Task File Register 1 register to clear the device
interrupt and determine if there was an error.
Write 1 to bit 18 of the PCI Bus Master – IDEx Register to clear the ATA interrupt.
If no error, repeat the write operation steps until all data for the write command has been
transferred or an error has been detected.
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0069-C
112
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