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參數(shù)資料
| 型號(hào)： | SiI0680ACL144 |
| 廠商： | Silicon Image, Inc. |
| 英文描述： | PCI to IDE/ATA |
| 中文描述： | PCI到IDE / ATA的 |
| 文件頁(yè)數(shù)： | 108/124頁(yè) |
| 文件大?。?/td> | 820K |
| 代理商： | SII0680ACL144 |
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SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0069-C
108
11. Programming Sequences
11.1 Recommended Initialization Sequence for the SiI 0680A
The recommended initialization sequence for the SiI 0680A is detailed below.
Initialize PCI Configuration Space registers
Initialize Base Address Register 0 with the address of an 8-byte range in I/O space.
Initialize Base Address Register 1 with the address of a 4-byte range in I/O space.
Initialize Base Address Register 2 with the address of an 8-byte range in I/O space.
Initialize Base Address Register 3 with the address of a 4-byte range in I/O space.
Initialize Base Address Register 4 with the address of a 16-byte range in I/O space.
Initialize Base Address Register 5 with the address of a 256-byte range in memory space.
To enable the bios expansion ROM, initialize the Expansion ROM Base Address Register with the
address of a 512KB range in memory space.
Enable I/O space access, memory space access, and bus master operation by setting bits [2:0] of the
PCI Command register.
NOTE: The preceding configuration space register initialization is normally done by the motherboard BIOS in PC
type systems.
Set IDE clock frequency by programming bits [21:20] of the System Configuration Status and Command register
at offset 88
H
in configuration space, or at base address 5, offset 48
H
.
If the PCI-IDE arbiter’s default FIFO read/write request thresholds are not suitable for the application they may
be changed via the FIFO Valid Byte Count and Control IDEx register. The read threshold is defined by bits
[05:00], and the write threshold is defined by bits [13:08] in the FIFO Valid Byte Count and Control – IDEx
register. In most environments, setting these bit fields to zero results in the best utilization of the PCI bus by the
680A controller.
If interrupt driven operation is
not
desired, set bits [23:22] of the System Configuration Status and Command
register to block IDE interrupts from reaching the PCI bus.
11.2 ATA/ATAPI Device Initialization
This section provides a general overview of the steps necessary to initialize an ATA/ATAPI device before it can be used for
read/write operations.
Select the ATA/ATAPI device. The device is selected by programming bits [23:16] in the IDEx Task File
Register 1 register.
If interrupt driven operation is desired, ensure that IDE interrupts are enabled by writing 0 to bits [23:16] of
the IDEx Task File Register 2 register.
For ATA devices only:
Issue the Initialize Device Parameters command by
Programming bits [23:16] in the IDEx Task File 0 register with the number of logical sectors
per logical track.
Programming bits [23:16] in the IDEx Task File 1 register with the maximum head number.
Programming bits [31:24] in the IDEx Task File Register 1 register with the value = 91
H
.
Wait for the command to complete. This can be accomplished by waiting for an interrupt if
interrupts have been enabled at both the controller and the device. If interrupts are not
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