參數(shù)資料
型號(hào)： SiI0680ACL144
廠商： Silicon Image, Inc.
英文描述： PCI to IDE/ATA
中文描述： PCI到IDE / ATA的
文件頁數(shù)： 69/124頁
文件大小： 820K
代理商： SII0680ACL144
Silicon Image, Inc.
SiI0680A PCI to IDE/ATA
Data Sheet
2006 Silicon Image, Inc.
SiI-DS-0069-C
69
9.7 Internal Register Space – Base Address 5
These registers are 32-bits wide and define the internal operation of the SiI 0680A. The access types are defined as follows:
R=read, W=write, and C=clearable by some write operation. Access to this register is through the PCI Memory space. The
Base Address 5 can be disabled by setting input BA5_EN to low
Register Name
Address
Offset
31
16
15
00
Access
Type
00
H
Reserved
PCI Bus Master
Status – IDE0
Software Data
PCI Bus Master
Command – IDE0
R/W
04
H
PRD Table Address – IDE0
R/W
08
H
Reserved
PCI Bus Master
Status – IDE1
Reserved
PCI Bus Master
Command – IDE1
R/W
0C
H
PRD Table Address – IDE1
R/W
10
H
PCI Bus Master
Status – IDE1
PCI Bus Master
Status2 – IDE0
Software Data
PCI Bus Master
Command2 –
IDE0
R/W
14
H
Reserved
-
18
H
Reserved
PCI Bus Master
Status2 – IDE1
Reserved
PCI Bus Master
Command2 –
IDE1
R/W
1C
H
Reserved
-
20
H
PRD Address – IDE0
R
24
H
PCI Bus Master Byte Count – IDE0
R
28
H
PRD Address – IDE1
R
2C
H
PCI Bus Master Byte Count – IDE1
R
30
H
Reserved
-
34
H
Reserved
-
38
H
Reserved
-
3C
H
Reserved
-
40
H
FIFO Valid Byte Count – IDE0
FIFO Wr Request
Control – IDE0
FIFO Rd Request
Control – IDE0
R/W
44
H
FIFO Valid Byte Count – IDE1
FIFO Wr Request
Control – IDE1
FIFO Rd Request
Control – IDE1
R/W
48
H
System Configuration Status
System Command
R/W
4C
H
System Software Data
R/W
50
H
FLASH Memory Address – Command and Status
R/W
54
H
Reserved
Flash Memory
Data
R/W
58
H
EEPROM Memory Address – Command and Status
R/W
5C
H
Reserved
EEPROM Memory
Data
R/W
60
H
FIFO Port – IDE0
R/W
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