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參數(shù)資料
| 型號(hào)： | SiI0680ACL144 |
| 廠商： | Silicon Image, Inc. |
| 英文描述： | PCI to IDE/ATA |
| 中文描述： | PCI到IDE / ATA的 |
| 文件頁(yè)數(shù)： | 119/124頁(yè) |
| 文件大?。?/td> | 820K |
| 代理商： | SII0680ACL144 |
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Silicon Image, Inc.
SiI0680A PCI to IDE/ATA
Data Sheet
2006 Silicon Image, Inc.
SiI-DS-0069-C
119
12.2 EEPROM Memory Access
The SiI 0680A supports an external 256-byte EEPROM memory device. Access to the EEPROM memory is available through
internal register operations in the SiI 0680A.
EEPROM Write Operation
Verify that bit 25 is cleared in the EEPROM Memory Address – Command + Status register at Offset 58
H
of
Base Address 5. The bit reads one when a memory access is currently in progress. It reads zero when the
memory access is complete and ready for another operation.
Write ‘1’ to clear bit 28 in the EEPROM Memory Address – Command + Status register. The bit is set if an
error occurred during a previous memory access.
Program the write address for the EEPROM memory access. The address field is defined by bits [07:00] in
the EEPROM Memory Address – Command + Status register. Program bits [15:08] to zero.
Program the write data for the EEPROM memory access. The data field is defined by bits [07:00] in the
EEPROM Memory Data register at Offset 5C
H
of Base Address 5.
Program the memory access type. The memory access type is defined by bit 24 in the EEPROM Memory
Address – Command + Status register. The bit must be cleared for a memory write access.
Initiate the EEPROM memory access by setting bit 25 in the EEPROM Memory Address – Command +
Status register.
Poll bit 25 in the EEPROM Memory Address – Command + Status register. The bit reads one when a
memory access is currently in progress. It reads zero when the memory access is complete.
Check bit 28 in the EEPROM Memory Address – Command + Status register. The bit is set if an error
occurred during a previous memory access.
EEPROM Read Operation
Verify that bit 25 is cleared in the EEPROM Memory Address – Command + Status register at Offset 58
H
of
Base Address 5. The bit reads one when a memory access is currently in progress. It reads zero when the
memory access is complete and ready for another operation.
Write ‘1’ to clear bit 28 in the EEPROM Memory Address – Command + Status register. The bit is set if an
error occurred during a previous memory access.
Program the read address for the EEPROM memory access. The address field is defined by bits [07:00] in
the EEPROM Memory Address – Command + Status register. Program bits [15:08] to zero.
Program the memory access type. The memory access type is defined by bit 24 in the EEPROM Memory
Address – Command + Status register. The bit must be set for a memory read access.
Initiate the EEPROM memory access by setting bit 25 in the EEPROM Memory Address – Command +
Status register.
Poll bit 25 in the EEPROM Memory Address – Command + Status register. The bit reads one when a
memory access is currently in progress. It reads zero when the memory access is complete.
Check bit 28 in the EEPROM Memory Address – Command + Status register. The bit is set if an error
occurred during a previous memory access.
Read the data from the EEPROM memory access. The data field is defined by bits [07:00] in the EEPROM
Memory Data register at Offset 5C
H
of Base Address 5.
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PDF描述 |
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| SiI0680ACLU144 | PCI to IDE/ATA |
| SII0680 | SteelVine⑩ Host Controller |
| SII1000 | PanelLink Receivers |
| SII1151 | TELECOMMANDER USB(PC&Mac OS X) FOR DESKTOP ROVER |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SII0680ACLU144 | 制造商:Silicon Image Inc 功能描述:STEELVINE HOST CONTROLLER |
| SII1000 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PanelLink Receivers |
| SII100N06 | 制造商:SIRECTIFIER 制造商全稱:Sirectifier Semiconductors 功能描述:NPT IGBT Modules |
| SII100N12 | 制造商:SIRECTIFIER 制造商全稱:Sirectifier Semiconductors 功能描述:NPT IGBT Modules |
| SII100S12 | 制造商:SIRECTIFIER 制造商全稱:Sirectifier Semiconductors 功能描述:絕緣柵雙極型晶體管（IGBT）Isolated Gate Bipolar Transistor (IGBTs)，SPT技術(shù)的IGBT模塊SPT IGBT Modules (Soft Punch Through Technology)。 |
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