參數(shù)資料
型號： SII0680A
廠商： Silicon Image, Inc.
英文描述： PCI to IDE/ATA
中文描述： PCI到IDE / ATA的
文件頁數(shù)： 90/124頁
文件大小： 820K
代理商： SII0680A
SiI0680A PCI to IDE/ATA
Data Sheet
9.7.34
IDE0 PIO Timing
Address Offset: A4
H
Access Type: Read/Write
Reset Value: 0x62DD_62DD
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0069-C
90
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Device 1 Addr
Setup Count
Device 1 Active Count
Device 1 Recovery
Count
Device 0 Addr
Setup Count
Device 0 Active Count
Device 0 Recovery
Count
This register defines the PIO timing register for IDE Channel #0 in the SiI 0680A. See chapter 11 for details on
programming this timing register. The register bits are defined below.
Bit [31:28]
: Device 1 Addr Setup Count (R/W) – IDE0 Device 1 Address Setup Time Count for PIO Mode. This
bit field is used for programming the address setup time relative to IDE0_DIOR_N and IDE0_DIOW_N in PIO
mode.
Bit [27:22]
: Device 1 Active Count (R/W) – IDE0 Device 1 DIOR_N and DIOW_N Active Time Count for PIO
Mode. This bit field is used for programming the active time of IDE0_DIOR_N and IDE0_DIOW_N in PIO mode.
Bit [21:16]
: Device 1 Recovery Count (R/W) – IDE0 Device 1 DIOR_N and DIOW_N Recovery Time Count for
PIO Mode. This bit field is used for programming the recovery time of IDE0_DIOR_N and IDE0_DIOW_N in PIO
mode.
Bit [15:12]
: Device 0 Addr Setup Count (R/W) – IDE0 Device 0 Address Setup Time Count for PIO Mode. This
bit field is used for programming the address setup time relative to IDE0_DIOR_N and IDE0_DIOW_N in PIO
mode
Bit [11:06]
: Device 0 Active Count (R/W) – IDE0 Device 0 DIOR_N and DIOW_N Active Time Count for PIO
Mode. This bit field is used for programming the active time of IDE0_DIOR_N and IDE0_DIOW_N in PIO mode.
Bit [05:00]
: Device 0 Recovery Count (R/W) – IDE0 Device 0 DIOR_N and DIOW_N Recovery Time Count for
PIO Mode. This bit field is used for programming the recovery time of IDE0_DIOR_N and IDE0_DIOW_N in PIO
mode.
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