參數(shù)資料
型號(hào)： SII0680A
廠商： Silicon Image, Inc.
英文描述： PCI to IDE/ATA
中文描述： PCI到IDE / ATA的
文件頁數(shù)： 50/124頁
文件大?。?/td> 820K
代理商： SII0680A
SiI0680A PCI to IDE/ATA
Data Sheet
9.1.4
BIST – Header Type – Latency Timer – Cache Line Size
Address Offset: 0C
H
Access Type: Read/Write
Reset Value: 0x0000_0000
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0069-C
50
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
BIST
Header Type
Latency Timer
Cache Line Size
This register defines the various control functions associated with the PCI bus. The register bits are defined below.
Bit [31:24]
: BIST (R). This bit field is hardwired to 00
H
.
Bit [23:16]
: Header Type (R). This bit field is hardwired to 00
H
.
Bit [15:08]
: Latency Timer (R/W). This bit field is used to specify the time in number of PCI clocks, the SiI
0680A as a master is still allowed to control the PCI bus after its GRANT_L is deasserted. The lower four bits
[0B:08] are hardwired to 0
H
, resulting in a time granularity of 16 clocks.
Bit [07:00]
: Cache Line Size (R/W). This bit field is
used to specify the system cacheline size in terms of 32-bit
words. The upper 2 bits are not used, resulting a maximum size of 64 32-bit words. With the SiI 0680A as a
master, initiating a read transaction, it issues PCI command Read Multiple in place , when empty space in its
FIFO is larger than the value programmed in this register.
9.1.5
Address Offset: 10
H
Access Type: Read/Write
Reset Value: 0x0000_0001
Base Address Register 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Base Address Register 0
Not Used
This register defines the addressing of various control functions within the SiI 0680A. The register bits are defined below.
Bit [31:03]
: Base Address Register 0 (R/W). This register defines the I/O Space base address for the IDE
Channel #0 task file registers.
Bit [02:00]
: Base Address Register 0 (R). This bit field is not used and is hardwired to 001
B
9.1.6
Address Offset: 14
H
Access Type: Read/Write
Reset Value: 0x0000_0001
Base Address Register 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Base Address Register 1
Not
Used
This register defines the addressing of various control functions within the SiI 0680A. The register bits are defined below.
Bit [31:02]
: Base Address Register 1 (R/W). This register defines the I/O Space base address for the IDE
Channel #0 Device Control- Alternate Status register.
Bit [01:00]
: Base Address Register 1 (R). This bit field is not used and is hardwired to 01
B
.
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