參數(shù)資料
型號： SII0680A
廠商： Silicon Image, Inc.
英文描述： PCI to IDE/ATA
中文描述： PCI到IDE / ATA的
文件頁數(shù)： 118/124頁
文件大小： 820K
代理商： SII0680A
SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0069-C
118
12. FLASH and EEPROM Programming Sequences
12.1 FLASH Memory Access
The SiI 0680A supports an external FLASH memory device up to 4 Mbits in capacity. Access to the FLASH memory is
available through two means: PCI Direct Access and Register Access.
12.1.1 PCI Direct Access
Access to the Expansion Rom is enabled by setting bit 0 in the Expansion Rom Base Address register at Offset 30h of the PCI
Configuration Space. When this bit is set, bits [31:19] of the same register are programmable by the system to set the base
address for all FLASH memory accesses. Read and write operations with the FLASH memory are initiated by Memory Read
and Memory Write commands on the PCI bus. Accesses may be as Bytes, Words, or DWords.
12.2.2 Register Access
This type of FLASH memory access is carried out through a sequence of internal register read and write operations. The
proper programming sequences are detailed below.
FLASH Write Operation
Verify that bit 25 is cleared in the register at Offset 50
H
of Base Address 5. The bit reads one when a
memory access is currently in progress.
It reads zero when the memory access is complete and ready for another operation.
Program the write address for the FLASH memory access. The address field is defined by bits [18:00] in the
FLASH Memory Address – Command + Status register.
Program the write data for the FLASH memory access. The data field is defined by bits [07:00] in the
FLASH Memory Data register at Offset 54 of Base Address 5.
Program the memory access type . The memory access type is defined by bit 24 in the FLASH Memory
Address – Command + Status register. The bit must be cleared for a memory write access.
Initiate the FLASH memory access by setting bit 25 in the FLASH Memory Address – Command + Status
register.
FLASH Read Operation
Verify that bit 25 is cleared in the FLASH Memory Address – Command + Status register at Offset 50
H
of
Base Address 5. The bit reads one when a memory access is currently in progress. It reads zero when the
memory access is complete and ready for another operation.
Program the read address for the FLASH memory access. The address field is defined by bits [18:00] in the
FLASH Memory Address – Command + Status register.
Program the memory access type. The memory access type is defined by bit 24 in the FLASH Memory
Address – Command + Status register. The bit must be set for a memory read access.
Initiate the FLASH memory access by setting bit 25 in the FLASH Memory Address – Command + Status
register.
Verify that bit 25 is cleared in the FLASH Memory Address – Command + Status register. The bit reads one
when a memory access is currently in progress. It reads zero when the memory access is complete.
Read the data from the FLASH memory access. The data field is defined by bits [07:00] in the FLASH
Memory Data register at Offset 54
H
of Base Address 5.
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